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GET /api/patches/96752/?format=api
{ "id": 96752, "url": "http://patchwork.dpdk.org/api/patches/96752/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210810025140.1698163-14-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210810025140.1698163-14-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210810025140.1698163-14-qi.z.zhang@intel.com", "date": "2021-08-10T02:51:25", "name": "[13/28] net/ice/base: implement firmware debug dump", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3e04c8507a2020158b9882e4e0d772df703d355f", "submitter": { "id": 504, "url": "http://patchwork.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210810025140.1698163-14-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18242, "url": "http://patchwork.dpdk.org/api/series/18242/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18242", "date": "2021-08-10T02:51:12", "name": "ice: base code update", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18242/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96752/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96752/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 26DAAA0C54;\n\tTue, 10 Aug 2021 04:50:00 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8F4E64116D;\n\tTue, 10 Aug 2021 04:49:12 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 515A14115C\n for <dev@dpdk.org>; Tue, 10 Aug 2021 04:49:11 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Aug 2021 19:49:10 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:49:01 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10070\"; a=\"202002170\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"202002170\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"483823674\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Marcin Domagala <marcinx.domagala@intel.com>", "Date": "Tue, 10 Aug 2021 10:51:25 +0800", "Message-Id": "<20210810025140.1698163-14-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "References": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 13/28] net/ice/base: implement firmware debug dump", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Basic implementation of FW Debug Dump.\n\nSigned-off-by: Marcin Domagala <marcinx.domagala@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 25 ++++++++++++++\n drivers/net/ice/base/ice_common.c | 50 +++++++++++++++++++++++++++\n drivers/net/ice/base/ice_common.h | 6 ++++\n 3 files changed, 81 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 74c4e8f120..7205fc6fbe 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -2720,6 +2720,27 @@ struct ice_aqc_event_lan_overflow {\n \tu8 reserved[8];\n };\n \n+/* Debug Dump Internal Data (indirect 0xFF08) */\n+struct ice_aqc_debug_dump_internals {\n+\tu8 cluster_id;\n+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW\t\t0\n+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL\t\t1\n+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED\t2\n+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES\t3\n+/* EMP_DRAM only dumpable in device debug mode */\n+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM\t4\n+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK\t5\n+/* AUX_REGS only dumpable in device debug mode */\n+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS\t6\n+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB\t7\n+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P\t8\n+\tu8 reserved;\n+\t__le16 table_id; /* Used only for non-memory clusters */\n+\t__le32 idx; /* In table entries for tables, in bytes for memory */\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n /* Set Health Status (direct 0xFF20) */\n struct ice_aqc_set_health_status_config {\n \tu8 event_source;\n@@ -2894,6 +2915,7 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_download_pkg download_pkg;\n \t\tstruct ice_aqc_get_pkg_info_list get_pkg_info_list;\n \t\tstruct ice_aqc_driver_shared_params drv_shared_params;\n+\t\tstruct ice_aqc_debug_dump_internals debug_dump;\n \t\tstruct ice_aqc_set_mac_lb set_mac_lb;\n \t\tstruct ice_aqc_alloc_free_res_cmd sw_res_ctrl;\n \t\tstruct ice_aqc_get_res_alloc get_res;\n@@ -3161,6 +3183,9 @@ enum ice_adminq_opc {\n \t/* Standalone Commands/Events */\n \tice_aqc_opc_event_lan_overflow\t\t\t= 0x1001,\n \n+\t/* debug commands */\n+\tice_aqc_opc_debug_dump_internals\t\t= 0xFF08,\n+\n \t/* SystemDiagnostic commands */\n \tice_aqc_opc_set_health_status_config\t\t= 0xFF20,\n \tice_aqc_opc_get_supported_health_status_codes\t= 0xFF21,\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 9cfff8930e..e98145bf3f 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -4517,6 +4517,56 @@ ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_aq_get_internal_data\n+ * @hw: pointer to the hardware structure\n+ * @cluster_id: specific cluster to dump\n+ * @table_id: table ID within cluster\n+ * @start: index of line in the block to read\n+ * @buf: dump buffer\n+ * @buf_size: dump buffer size\n+ * @ret_buf_size: return buffer size (returned by FW)\n+ * @ret_next_table: next block to read (returned by FW)\n+ * @ret_next_index: next index to read (returned by FW)\n+ * @cd: pointer to command details structure\n+ *\n+ * Get internal FW/HW data (0xFF08) for debug purposes.\n+ */\n+enum ice_status\n+ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,\n+\t\t\t u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,\n+\t\t\t u16 *ret_next_table, u32 *ret_next_index,\n+\t\t\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_debug_dump_internals *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.debug_dump;\n+\n+\tif (buf_size == 0 || !buf)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_debug_dump_internals);\n+\n+\tcmd->cluster_id = cluster_id;\n+\tcmd->table_id = CPU_TO_LE16(table_id);\n+\tcmd->idx = CPU_TO_LE32(start);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\n+\tif (!status) {\n+\t\tif (ret_buf_size)\n+\t\t\t*ret_buf_size = LE16_TO_CPU(desc.datalen);\n+\t\tif (ret_next_table)\n+\t\t\t*ret_next_table = LE16_TO_CPU(cmd->table_id);\n+\t\tif (ret_next_index)\n+\t\t\t*ret_next_index = LE32_TO_CPU(cmd->idx);\n+\t}\n+\n+\treturn status;\n+}\n+\n /**\n * ice_read_byte - read context byte into struct\n * @src_ctx: the context structure to read from\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex a18cccd8cb..770db8f40c 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -64,6 +64,12 @@ enum ice_status ice_get_caps(struct ice_hw *hw);\n \n void ice_set_safe_mode_caps(struct ice_hw *hw);\n \n+enum ice_status\n+ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,\n+\t\t\t u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,\n+\t\t\t u16 *ret_next_table, u32 *ret_next_index,\n+\t\t\t struct ice_sq_cd *cd);\n+\n /* Define a macro that will align a pointer to point to the next memory address\n * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For\n * example, given the variable pointer = 0x1006, then after the following call:\n", "prefixes": [ "13/28" ] }