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GET /api/patches/96757/?format=api
{ "id": 96757, "url": "http://patchwork.dpdk.org/api/patches/96757/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210810025140.1698163-19-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210810025140.1698163-19-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210810025140.1698163-19-qi.z.zhang@intel.com", "date": "2021-08-10T02:51:30", "name": "[18/28] net/ice/base: support RSS for GRE tunnel packet", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d24824ff868847500631dd3eeb9b7544d4b338f4", "submitter": { "id": 504, "url": "http://patchwork.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210810025140.1698163-19-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18242, "url": "http://patchwork.dpdk.org/api/series/18242/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18242", "date": "2021-08-10T02:51:12", "name": "ice: base code update", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18242/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96757/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96757/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 62435A0C54;\n\tTue, 10 Aug 2021 04:50:29 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0A93A411D3;\n\tTue, 10 Aug 2021 04:49:23 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 1E1E04118D\n for <dev@dpdk.org>; Tue, 10 Aug 2021 04:49:20 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Aug 2021 19:49:20 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:49:19 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10070\"; a=\"202002188\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"202002188\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"483823750\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Wenjun Wu <wenjun1.wu@intel.com>", "Date": "Tue, 10 Aug 2021 10:51:30 +0800", "Message-Id": "<20210810025140.1698163-19-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "References": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 18/28] net/ice/base: support RSS for GRE tunnel\n packet", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Support RSS of inner headers for GRE tunnel packet.\n\nSigned-off-by: Wenjun Wu <wenjun1.wu@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flow.c | 14 ++++++--------\n 1 file changed, 6 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex b336275d0c..5b26d6c8b2 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -257,7 +257,7 @@ static const u32 ice_ptypes_ipv4_ofos[] = {\n * includes IPV4 other PTYPEs\n */\n static const u32 ice_ptypes_ipv4_ofos_all[] = {\n-\t0x1D800000, 0x24000800, 0x00000000, 0x00000000,\n+\t0x1D800000, 0x27BF7800, 0x00000000, 0x00000000,\n \t0x00000000, 0x00000155, 0x00000000, 0x00000000,\n \t0x00000000, 0x000FC000, 0x83E0FAA0, 0x00000101,\n \t0x03FFD500, 0x00000000, 0x00000000, 0x00000000,\n@@ -297,7 +297,7 @@ static const u32 ice_ptypes_ipv6_ofos[] = {\n * includes IPV6 other PTYPEs\n */\n static const u32 ice_ptypes_ipv6_ofos_all[] = {\n-\t0x00000000, 0x00000000, 0x76000000, 0x10002000,\n+\t0x00000000, 0x00000000, 0x76000000, 0x1EFDE000,\n \t0x00000000, 0x000002AA, 0x00000000, 0x00000000,\n \t0x00000000, 0x03F00000, 0x7C1F0540, 0x00000206,\n \t0xFC002A00, 0x0000003F, 0x00000000, 0x00000000,\n@@ -807,7 +807,7 @@ struct ice_flow_prof_params {\n \tICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \\\n \tICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP | \\\n \tICE_FLOW_SEG_HDR_ECPRI_TP0 | ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0 | \\\n-\tICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP)\n+\tICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP | ICE_FLOW_SEG_HDR_GRE)\n \n #define ICE_FLOW_SEG_HDRS_L2_MASK\t\\\n \t(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)\n@@ -1024,11 +1024,9 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)\n \t\t\tice_and_bitmap(params->ptypes, params->ptypes, src,\n \t\t\t\t ICE_FLOW_PTYPE_MAX);\n \t\t} else if (hdrs & ICE_FLOW_SEG_HDR_GRE) {\n-\t\t\tif (!i) {\n-\t\t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_gre_of;\n-\t\t\t\tice_and_bitmap(params->ptypes, params->ptypes,\n-\t\t\t\t\t src, ICE_FLOW_PTYPE_MAX);\n-\t\t\t}\n+\t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_gre_of;\n+\t\t\tice_and_bitmap(params->ptypes, params->ptypes, src,\n+\t\t\t\t ICE_FLOW_PTYPE_MAX);\n \t\t} else if (hdrs & ICE_FLOW_SEG_HDR_GTPC) {\n \t\t\tsrc = (const ice_bitmap_t *)ice_ptypes_gtpc;\n \t\t\tice_and_bitmap(params->ptypes, params->ptypes,\n", "prefixes": [ "18/28" ] }