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GET /api/patches/96760/?format=api
{ "id": 96760, "url": "http://patchwork.dpdk.org/api/patches/96760/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210810025140.1698163-22-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210810025140.1698163-22-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210810025140.1698163-22-qi.z.zhang@intel.com", "date": "2021-08-10T02:51:33", "name": "[21/28] net/ice/base: enable NVM update reset capabilities", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fc82dc0e640df18d9a6f44b131e780999a1d26f8", "submitter": { "id": 504, "url": "http://patchwork.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210810025140.1698163-22-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18242, "url": "http://patchwork.dpdk.org/api/series/18242/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18242", "date": "2021-08-10T02:51:12", "name": "ice: base code update", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18242/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96760/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96760/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E4843A0C54;\n\tTue, 10 Aug 2021 04:50:45 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3D71A411E5;\n\tTue, 10 Aug 2021 04:49:28 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 6980D411D0\n for <dev@dpdk.org>; Tue, 10 Aug 2021 04:49:26 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Aug 2021 19:49:26 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:49:24 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10070\"; a=\"202002199\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"202002199\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"483823776\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>", "Date": "Tue, 10 Aug 2021 10:51:33 +0800", "Message-Id": "<20210810025140.1698163-22-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "References": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 21/28] net/ice/base: enable NVM update reset\n capabilities", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add logic to parse capabilities relating to the firmware update reset\nrequirements. This includes both capability 0x76, which informs the\ndriver if the firmware can sometimes skip PCIe resets, and 0x77, which\ninforms the driver if the firmware might potentially restrict EMP\nresets.\n\nFor capability 0x76, if the number is 1, the firmware will report the\nrequired reset level for a given update as part of its response to the\nlast command sent to program the NVM bank. (Otherwise, if the firmware\ndoes not support this capability then it will always send a 0 in the\nfield of the response).\n\nFor capability 0x77, if the number is 1, the firmware will report when\nEMP reset is available as part of the response to the command for\nswitching flash banks. (Otherwise, if the firmware does not support this\ncapability, it will always send a 0 in the field of the response\nmessage).\n\nThese capabilities are required to implement immediate firmware\nactivation. If the capabilities are set, software can read the response\ndata and determine what reset level is required to activate the firmware\nimage. If only an EMP reset is required, and if the EMP reset is not\nrestricted by firmware, then the driver can issue an EMP reset to\nimmediately activate the new firmware.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 12 ++++++++++++\n drivers/net/ice/base/ice_type.h | 4 ++++\n 2 files changed, 16 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex a77bf32b1c..2744c3d119 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -2281,6 +2281,18 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,\n \t\tice_debug(hw, ICE_DBG_INIT, \"%s: max_mtu = %d\\n\",\n \t\t\t prefix, caps->max_mtu);\n \t\tbreak;\n+\tcase ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:\n+\t\tcaps->pcie_reset_avoidance = (number > 0);\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: pcie_reset_avoidance = %d\\n\", prefix,\n+\t\t\t caps->pcie_reset_avoidance);\n+\t\tbreak;\n+\tcase ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:\n+\t\tcaps->reset_restrict_support = (number == 1);\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: reset_restrict_support = %d\\n\", prefix,\n+\t\t\t caps->reset_restrict_support);\n+\t\tbreak;\n \tcase ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0:\n \tcase ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1:\n \tcase ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2:\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex b76404f085..6ae39a345b 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -480,6 +480,10 @@ struct ice_hw_common_caps {\n #define ICE_NVM_MGMT_SEC_REV_DISABLED\t\tBIT(0)\n #define ICE_NVM_MGMT_UPDATE_DISABLED\t\tBIT(1)\n #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT\tBIT(3)\n+\t/* PCIe reset avoidance */\n+\tbool pcie_reset_avoidance; /* false: not supported, true: supported */\n+\t/* Post update reset restriction */\n+\tbool reset_restrict_support; /* false: not supported, true: supported */\n \n \t/* External topology device images within the NVM */\n #define ICE_EXT_TOPO_DEV_IMG_COUNT\t4\n", "prefixes": [ "21/28" ] }