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GET /api/patches/96831/?format=api
{ "id": 96831, "url": "http://patchwork.dpdk.org/api/patches/96831/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210812071244.28799-10-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210812071244.28799-10-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210812071244.28799-10-hemant.agrawal@nxp.com", "date": "2021-08-12T07:12:37", "name": "[RFC,09/16] crypto/dpaa2_sec: support OOP with raw buffer API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ccba3f00de6ea4a4f10250133c9ea5c487744578", "submitter": { "id": 477, "url": "http://patchwork.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210812071244.28799-10-hemant.agrawal@nxp.com/mbox/", "series": [ { "id": 18259, "url": "http://patchwork.dpdk.org/api/series/18259/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18259", "date": "2021-08-12T07:12:28", "name": "crypto: add raw vector support in DPAAx", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18259/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96831/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/96831/checks/", "tags": {}, "related": [], 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b=ocYNrqnoULxqZ4937D+XfLkOuocsjfUulQt3QLGsu5eJbPMPXIQyYbO9jyG61e42nYHC2T0xL4nkF61pJdlHodzr7HQ3zjv8GJiZGJEW6m3yAoe+tIU7oqZS2a4GOsWICnQAOkMzSDAx0UZOCmpA+7jynfssexrB+muEENZlvYk=", "Authentication-Results": "dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=none action=none header.from=nxp.com;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "dev@dpdk.org,\n\tgakhil@marvell.com", "Cc": "Gagandeep Singh <g.singh@nxp.com>", "Date": "Thu, 12 Aug 2021 12:42:37 +0530", "Message-Id": "<20210812071244.28799-10-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210812071244.28799-1-hemant.agrawal@nxp.com>", "References": "<20210812071244.28799-1-hemant.agrawal@nxp.com>", "Content-Type": "text/plain", "X-ClientProxiedBy": "SG2PR02CA0105.apcprd02.prod.outlook.com\n (2603:1096:4:92::21) To DU2PR04MB8630.eurprd04.prod.outlook.com\n (2603:10a6:10:2dd::15)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", 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RIdEGzu5hjKl72G65lZEOxfx9araPTFti32KLQXvUDPqslIFEC6/uItidp9nwEP2dIP60BEMJnW3z463LHWuYo/HRqtqiMHMUgWFhH9Gejxl1asRy0SvCjVEdRF5588Up7+3T/E0ia3A+gAtfDKT6qXgIieXLisAW9LEKbNczuRCUMzrzpmMD/GkSaXrOV+/rotsK94fLPub2mTBziovSlcfHrrX4FsUUoyM5OmcV8jfzWLMacXRlbwN7JEi7H5tBYLGK+V1lMIUQu3xOYVxyk+LK0jRYGD44NVmj4EcAi2rVekWcIlAcWQYEzByI5pw8N+IwUcPt7AFFNNwnXhSZCVWW9nVpQFR3LWNSEj7xlJdj+5qBGE0ax1Gq4+Iou/LCJTXALpY1VCTuplwrwPkoaHGRR2gkf7c+4pflm+3C2ZtB/inpGUmiTla2S3FH6+NAvyOz3ZNrCbukxD6pU6MrtFVhWtn/3LsI4Ex8DeEBGF7trCWj8OG1U/a3kPGonemI0KSsIYr2BrekzZgd3rlSJacQw5B14b26Vn5hj0E6e+0nBmb/uA2lfq5yS/0dSOVG1vIGiT1JD6FzPfK7rS42Cg8f1RQNz44wEELSzJFLvhw7j58WRrP09bKa/sc3doe1aOoFtBE8VkB88VxSzws4atrIWfNUVC1+C+9TahfRRAPWUne8zBc2c4jLbn7dTgXTvPVYTX3k9mHLKu4y8QpVr1PzafrbNrKsyq/Lg92wsfkNj4+9a36ue+A/+h/z4+2Rr/Jk6TEdZQLEBH+3qUrJl7AeLlH4etlvCfgJvfwnsERI6dgTXEQ+hL7cORcGMUSvRPhIowBhz3km+Ip+BWNHwAPCkGcnmw4aqF4fgq3SSSHJd3w+2ZvAGiJs1mVLnl1lLat0ZIoGe8g6IZdJbZJc9+gQqwgTu9q8lago69dv21VRRMQYFSQI4RvjyvzcwJ/tLIQBfXaC+GvHf7gbW1AP0AtstNYg3AOp5m9lwBgV8iBVgJmxAvuZQc9/uc0MZq7JsllHmS5GAXji+q0CW/WB1Sij8X9QvbB8Rgj37W2an44ay7LGaSfO5nq79tRS9fcduhqJuKwVfbo2ZYD+5w7Uo0I53hTlMF90Eea0+819qIQhU8biKtDeTgmNGdodkJ9cRO4PZud6BMLC0SOrjV6w5ORW9aBojB7oY6Vk1wdKkuQhfpCAcmaVfJ3x1Wrw0+WwRJfwep+HzvytLEFCjphNlV21J0aL/iNpLj2G89EO5SxxgG8zoPisuQJ1yIfVGXpxbAzRt0pDsrV41MpA/A2d7MOW65mvddBI/ApJWcJMIjepLudS9a0SKjYKi7e3khm", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6a1ecf4a-bdc9-4674-8f80-08d95d611524", "X-MS-Exchange-CrossTenant-AuthSource": "DU2PR04MB8630.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Aug 2021 07:16:19.9525 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 4WgON3vpZITnhHHbpBKOqHbe3w+BByJ79VDBvkRqjXm4jqbCnnyw8EKsZZCuxunJ3/1E1j4wGFNv2b937zbAdA==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB9PR04MB8461", "Subject": "[dpdk-dev] [RFC 09/16] crypto/dpaa2_sec: support OOP with raw\n buffer API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Gagandeep Singh <g.singh@nxp.com>\n\nadd support for out of order processing with raw vector APIs.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 1 +\n drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c | 156 +++++++++++++++-----\n 2 files changed, 116 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\nindex f6507855e3..db72c11a5f 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n@@ -179,6 +179,7 @@ typedef int (*dpaa2_sec_build_fd_t)(\n \n typedef int (*dpaa2_sec_build_raw_dp_fd_t)(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\nindex 41f24c93b6..87a1a10268 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\n@@ -24,6 +24,7 @@ struct dpaa2_sec_raw_dp_ctx {\n static int\n build_raw_dp_chain_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -89,17 +90,33 @@ build_raw_dp_chain_fd(uint8_t *drv_ctx,\n \t\t\t(cipher_len + icv_len) :\n \t\t\tcipher_len;\n \n-\t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.auth.head);\n-\tsge->length = sgl->vec[0].len - ofs.ofs.auth.head;\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = dest_sgl->vec[0].len - ofs.ofs.cipher.head;\n \n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n+\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t}\n \t}\n \n \tif (sess->dir == DIR_ENC) {\n@@ -160,6 +177,7 @@ build_raw_dp_chain_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_aead_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -219,17 +237,33 @@ build_raw_dp_aead_fd(uint8_t *drv_ctx,\n \t\t\t(aead_len + icv_len) :\n \t\t\taead_len;\n \n-\t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n-\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = dest_sgl->vec[0].len - ofs.ofs.cipher.head;\n \n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n+\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t}\n \t}\n \n \tif (sess->dir == DIR_ENC) {\n@@ -294,6 +328,7 @@ build_raw_dp_aead_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_auth_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -303,6 +338,7 @@ build_raw_dp_auth_fd(uint8_t *drv_ctx,\n {\n \tRTE_SET_USED(iv);\n \tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(dest_sgl);\n \n \tdpaa2_sec_session *sess =\n \t\t((struct dpaa2_sec_raw_dp_ctx *)drv_ctx)->session;\n@@ -416,6 +452,7 @@ build_raw_dp_auth_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_proto_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -466,20 +503,39 @@ build_raw_dp_proto_fd(uint8_t *drv_ctx,\n \tDPAA2_SET_FLE_SG_EXT(op_fle);\n \tDPAA2_SET_FLE_ADDR(op_fle, DPAA2_VADDR_TO_IOVA(sge));\n \n-\t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\tsge->length = sgl->vec[0].len;\n-\tout_len += sge->length;\n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n \t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\tsge->length = dest_sgl->vec[0].len;\n+\t\tout_len += sge->length;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t\tout_len += sge->length;\n+\t\t}\n+\t\tsge->length = dest_sgl->vec[i - 1].tot_len;\n+\n+\t} else {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\tsge->length = sgl->vec[0].len;\n \t\tout_len += sge->length;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t\tout_len += sge->length;\n+\t\t}\n+\t\tsge->length = sgl->vec[i - 1].tot_len;\n \t}\n-\tsge->length = sgl->vec[i - 1].tot_len;\n \tout_len += sge->length;\n \n \tDPAA2_SET_FLE_FIN(sge);\n@@ -528,6 +584,7 @@ build_raw_dp_proto_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_cipher_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -593,17 +650,33 @@ build_raw_dp_cipher_fd(uint8_t *drv_ctx,\n \top_fle->length = data_len;\n \tDPAA2_SET_FLE_SG_EXT(op_fle);\n \n-\t/* o/p 1st seg */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n-\tsge->length = sgl->vec[0].len - data_offset;\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* o/p 1st seg */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\t\tsge->length = dest_sgl->vec[0].len - data_offset;\n \n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* o/p 1st seg */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\t\tsge->length = sgl->vec[0].len - data_offset;\n+\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t}\n \t}\n \tDPAA2_SET_FLE_FIN(sge);\n \n@@ -706,6 +779,7 @@ dpaa2_sec_raw_enqueue_burst(void *qp_data, uint8_t *drv_ctx,\n \t\t\tmemset(&fd_arr[loop], 0, sizeof(struct qbman_fd));\n \t\t\tret = sess->build_raw_dp_fd(drv_ctx,\n \t\t\t\t\t\t &vec->src_sgl[loop],\n+\t\t\t\t\t\t &vec->dest_sgl[loop],\n \t\t\t\t\t\t &vec->iv[loop],\n \t\t\t\t\t\t &vec->digest[loop],\n \t\t\t\t\t\t &vec->auth_iv[loop],\n", "prefixes": [ "RFC", "09/16" ] }