Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/97001/?format=api
{ "id": 97001, "url": "http://patchwork.dpdk.org/api/patches/97001/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210817134441.1966618-12-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210817134441.1966618-12-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210817134441.1966618-12-michaelba@nvidia.com", "date": "2021-08-17T13:44:31", "name": "[RFC,11/21] net/mlx5: move NUMA node field to context device", "commit_ref": null, "pull_url": null, "state": "rfc", "archived": true, "hash": "a9bbdf90c27a7bfebb340a9fc9683e9772327e52", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210817134441.1966618-12-michaelba@nvidia.com/mbox/", "series": [ { "id": 18314, "url": "http://patchwork.dpdk.org/api/series/18314/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18314", "date": "2021-08-17T13:44:20", "name": "mlx5: sharing global MR cache between drivers", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18314/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/97001/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/97001/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 92F5EA0548;\n\tTue, 17 Aug 2021 15:46:50 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8C461411FD;\n\tTue, 17 Aug 2021 15:45:37 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2065.outbound.protection.outlook.com [40.107.236.65])\n by mails.dpdk.org (Postfix) with ESMTP id 11078411FD\n for <dev@dpdk.org>; Tue, 17 Aug 2021 15:45:36 +0200 (CEST)", "from BN9PR03CA0254.namprd03.prod.outlook.com (2603:10b6:408:ff::19)\n by DM5PR12MB1706.namprd12.prod.outlook.com (2603:10b6:3:10f::7) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4415.19; Tue, 17 Aug\n 2021 13:45:34 +0000", "from BN8NAM11FT005.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:ff:cafe::7f) by BN9PR03CA0254.outlook.office365.com\n (2603:10b6:408:ff::19) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4415.17 via Frontend\n Transport; Tue, 17 Aug 2021 13:45:34 +0000", "from mail.nvidia.com (216.228.112.35) by\n BN8NAM11FT005.mail.protection.outlook.com (10.13.176.69) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4415.16 via Frontend Transport; Tue, 17 Aug 2021 13:45:34 +0000", "from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL111.nvidia.com\n (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug\n 2021 13:45:33 +0000", "from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com\n (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 17 Aug\n 2021 13:45:31 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=LclanSLVL663JP128D/o9eKO9U3+ba9h6jsqz+yqkWHnTB0lUurZObOWuOa6sJo+IKTfK9cH2b28KPPyd6Y9WOaRSy3b+IqHTcDB68fFySySmOu+GFt+k9JfR10Dl8fw1UE5eOPxh3dtJLbPCjJRmH+xw5tSJC2F4Y/odhQ5MxG9n8lXjHTYiWyHollXaQxlVpXnYmcgcbUPKBwS/AwiZcBSyNbCG8HLnA25mHFfjkFK99b480uF7/8BrZhcy/0x/8zR3RznStnnINaRg+3Li6Z8l6recSX9cq3RV84IYB20aLAFxDbWjNQXgGPxBkbgG+cRxBn71QyXmBR+CPj9TQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=LusB84Gbn+n0O0fsM07rjREfcejrLsEJMUgXr2I7OYg=;\n b=hXWxGXYCTyfvwM7XJBM8SF/QNCNFX0l+vt4Y3kVPByqsgiYdl9LQ361JhLIBdrZWFCYpoLkGhlWHjSI6gJ9+Al3y42gQ+4tvhnAq/epilPtO3ebkUmRMHjZsAJBYyr3WK2R7RSOjOb2ODXT6UW8ohTbtINHLulqfLEQ0xU0QjrG0tvWi1iXyb5RG/PKD0Tcos0hzioTM7gWrweUDF2fjFaXXMQafv9YJVW2DxtyzFbDITkvV9xVzulgV5RJjQkKlYPHs9tDbZikjx/5fiiGnBf0C0wFUlyzfsKoxWAXTJqxca/LVXImz1bxbXsMrZtxVEdaCetkZUYfyuNTvi/JvBA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.35) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=LusB84Gbn+n0O0fsM07rjREfcejrLsEJMUgXr2I7OYg=;\n b=VxLTd6NO2pCGQu16svtKlm0n2bK8anrK2rjfQ7WiiEQm8dBL03Yp61joPjstEMu0s8bdLtjji70RN91Kw+EfdmUP6xtDP5o4RoAbzbispnjlyR7wHRfy64RC4HYHD7vvqJz6QazVD08eLF0zidPfLPcZBGFHJBDTuaO/rpoAdvpw9fh+EiYtrf6fp4FxkMCFJmk8l4KEN3XVK9PBQSPbvxRPu9kqtxIcikk4v2vd/gH5+0t/rIOA5NrMDlLH/1NWgk3sLhlDntuvjQtvhwOh8/dadCtWUIIw5FX9E/2gutUbM8mfLCPi12vnN61tiV0DgYNXvuoTMXRxsm/N6ap2fw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.35)\n smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.35 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.35; helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Tue, 17 Aug 2021 16:44:31 +0300", "Message-ID": "<20210817134441.1966618-12-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210817134441.1966618-1-michaelba@nvidia.com>", "References": "<20210817134441.1966618-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n DRHQMAIL107.nvidia.com (10.27.9.16)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "42837e17-219f-4d54-093a-08d96185499e", "X-MS-TrafficTypeDiagnostic": "DM5PR12MB1706:", "X-Microsoft-Antispam-PRVS": "\n <DM5PR12MB1706690C75FFB3898AEB174DCCFE9@DM5PR12MB1706.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:473;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n CXFPDLimDGfTbkDEuusyhSl0ka8AKn0TCKwGDijC7e3d2M4UsGJvUdlj7b21YtiG7R9YWPeIA776BiiDOF1TsRxpN1v0iVCqO/ySKX8/roDxHPa93rcuT6D6kQrBrtcJQfzbG4ZDZq2PjFH+wxNjnqEoJN+vLI4+ha+0c8c/U/FixUAbhQl9qnWeRoq2wNMEqZGKuVEPt00JeLhOzgKrRKvoEnyx3UQ/hK1vFrwTbAxMaGH4V85G07pNEyy3L8aIbnXm5Mjq99soNgTbpsk+BCYoEXIrVKcufGvopeH/vS+Jbo3QSa9PYJRjsjRynmpysTMPxG0maHX7ktfGuJl8mofl/edrvWmrGgDw9xRH7scDgFRm1Tg1Wjel5B8fuKLOENNzkevchEGi4RzcIJT2eFE3D6XLZbcA6GUvMNppu49rgbxLkrbOmctNMrttp7wejoPLy9a3TEtUZ5cjLq8NY4FeYiaATO+hz1nn0x3X0GvF+gUP3ZIoP2G5G3jhSOdXpYAv+a9l/rcJ5fsdLL612iUtYEM4qmU5QmMUzdrXNM7q5VBADJrwFSgUoi3929v6UpYvv9AF4uRUtayoDm7rJdEvuAzOVEMVd//v9/reCbgJOQ30rBwehaJniUlueODQVRsbNtfwDJOrC44po6BZwVzze5supGw/qhVHovpT7B9IEQQCTdbkqJeNVBWebwBhdK/61u0Yv7KU+C7MO6XPdw==", "X-Forefront-Antispam-Report": "CIP:216.228.112.35; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid02.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(136003)(396003)(346002)(376002)(36840700001)(46966006)(86362001)(26005)(7696005)(186003)(16526019)(2616005)(8676002)(8936002)(478600001)(36860700001)(82740400003)(47076005)(316002)(82310400003)(36756003)(356005)(6286002)(1076003)(7636003)(83380400001)(54906003)(107886003)(70206006)(336012)(4326008)(5660300002)(426003)(70586007)(2906002)(6916009)(55016002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Aug 2021 13:45:34.1615 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 42837e17-219f-4d54-093a-08d96185499e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT005.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR12MB1706", "Subject": "[dpdk-dev] [RFC 11/21] net/mlx5: move NUMA node field to context\n device", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Remove numa node field from sh structure, and use instead in context\ndevice structure.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 3 +--\n drivers/net/mlx5/mlx5.h | 1 -\n drivers/net/mlx5/mlx5_devx.c | 11 ++++++-----\n drivers/net/mlx5/mlx5_txpp.c | 10 +++++-----\n 4 files changed, 12 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex f5f325d35a..b695f2f6d3 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1142,7 +1142,6 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\tgoto exit;\n \t}\n \tsh->devx = config->devx;\n-\tsh->numa_node = dev_ctx->numa_node;\n \tif (spawn->bond_info)\n \t\tsh->bond = *spawn->bond_info;\n \tpthread_mutex_init(&sh->txpp.mutex, NULL);\n@@ -1207,7 +1206,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t */\n \terr = mlx5_mr_btree_init(&sh->share_cache.cache,\n \t\t\t\t MLX5_MR_BTREE_CACHE_N * 2,\n-\t\t\t\t sh->numa_node);\n+\t\t\t\t dev_ctx->numa_node);\n \tif (err) {\n \t\terr = rte_errno;\n \t\tgoto error;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 1e52b9ac9a..f6d8e1d817 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1145,7 +1145,6 @@ struct mlx5_dev_ctx_shared {\n \tchar ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */\n \tchar ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */\n \tstruct mlx5_dev_attr device_attr; /* Device properties. */\n-\tint numa_node; /* Numa node of backing physical device. */\n \tLIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;\n \t/**< Called by memory event callback. */\n \tstruct mlx5_mr_share_cache share_cache;\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 3cafd46837..787c771167 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -366,7 +366,7 @@ mlx5_rxq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx)\n \tlog_cqe_n = log2above(cqe_n);\n \t/* Create CQ using DevX API. */\n \tret = mlx5_devx_cq_create(sh->dev_ctx->ctx, &rxq_ctrl->obj->cq_obj,\n-\t\t\t\t log_cqe_n, &cq_attr, sh->numa_node);\n+\t\t\t\t log_cqe_n, &cq_attr, sh->dev_ctx->numa_node);\n \tif (ret)\n \t\treturn ret;\n \tcq_obj = &rxq_ctrl->obj->cq_obj;\n@@ -981,6 +981,7 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,\n \t\t\t\t uint16_t log_desc_n)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx *dev_ctx = priv->sh->dev_ctx;\n \tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n \tstruct mlx5_txq_ctrl *txq_ctrl =\n \t\t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n@@ -994,15 +995,15 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,\n \t\t.tis_lst_sz = 1,\n \t\t.tis_num = priv->sh->tis->id,\n \t\t.wq_attr = (struct mlx5_devx_wq_attr){\n-\t\t\t.pd = priv->sh->dev_ctx->pdn,\n+\t\t\t.pd = dev_ctx->pdn,\n \t\t\t.uar_page =\n \t\t\t\t mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar),\n \t\t},\n \t\t.ts_format = mlx5_ts_format_conv(priv->sh->sq_ts_format),\n \t};\n \t/* Create Send Queue object with DevX. */\n-\treturn mlx5_devx_sq_create(priv->sh->dev_ctx->ctx, &txq_obj->sq_obj,\n-\t\t\t\t log_desc_n, &sq_attr, priv->sh->numa_node);\n+\treturn mlx5_devx_sq_create(dev_ctx->ctx, &txq_obj->sq_obj, log_desc_n,\n+\t\t\t\t &sq_attr, dev_ctx->numa_node);\n }\n #endif\n \n@@ -1059,7 +1060,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \t}\n \t/* Create completion queue object with DevX. */\n \tret = mlx5_devx_cq_create(sh->dev_ctx->ctx, &txq_obj->cq_obj,\n-\t\t\t\t log_desc_n, &cq_attr, sh->numa_node);\n+\t\t\t\t log_desc_n, &cq_attr, sh->dev_ctx->numa_node);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Port %u Tx queue %u CQ creation failure.\",\n \t\t\tdev->data->port_id, idx);\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex ff1c3d204c..b49a47bd77 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -247,7 +247,7 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n \t/* Create completion queue object for Rearm Queue. */\n \tret = mlx5_devx_cq_create(sh->dev_ctx->ctx, &wq->cq_obj,\n \t\t\t\t log2above(MLX5_TXPP_REARM_CQ_SIZE), &cq_attr,\n-\t\t\t\t sh->numa_node);\n+\t\t\t\t sh->dev_ctx->numa_node);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to create CQ for Rearm Queue.\");\n \t\treturn ret;\n@@ -261,7 +261,7 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)\n \t/* There should be no WQE leftovers in the cyclic queue. */\n \tret = mlx5_devx_sq_create(sh->dev_ctx->ctx, &wq->sq_obj,\n \t\t\t\t log2above(MLX5_TXPP_REARM_SQ_SIZE), &sq_attr,\n-\t\t\t\t sh->numa_node);\n+\t\t\t\t sh->dev_ctx->numa_node);\n \tif (ret) {\n \t\trte_errno = errno;\n \t\tDRV_LOG(ERR, \"Failed to create SQ for Rearm Queue.\");\n@@ -401,7 +401,7 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)\n \tsh->txpp.tsa = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n \t\t\t\t MLX5_TXPP_REARM_SQ_SIZE *\n \t\t\t\t sizeof(struct mlx5_txpp_ts),\n-\t\t\t\t 0, sh->numa_node);\n+\t\t\t\t 0, sh->dev_ctx->numa_node);\n \tif (!sh->txpp.tsa) {\n \t\tDRV_LOG(ERR, \"Failed to allocate memory for CQ stats.\");\n \t\treturn -ENOMEM;\n@@ -411,7 +411,7 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)\n \t/* Create completion queue object for Clock Queue. */\n \tret = mlx5_devx_cq_create(sh->dev_ctx->ctx, &wq->cq_obj,\n \t\t\t\t log2above(MLX5_TXPP_CLKQ_SIZE), &cq_attr,\n-\t\t\t\t sh->numa_node);\n+\t\t\t\t sh->dev_ctx->numa_node);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to create CQ for Clock Queue.\");\n \t\tgoto error;\n@@ -448,7 +448,7 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)\n \tsq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format);\n \tret = mlx5_devx_sq_create(sh->dev_ctx->ctx, &wq->sq_obj,\n \t\t\t\t log2above(wq->sq_size),\n-\t\t\t\t &sq_attr, sh->numa_node);\n+\t\t\t\t &sq_attr, sh->dev_ctx->numa_node);\n \tif (ret) {\n \t\trte_errno = errno;\n \t\tDRV_LOG(ERR, \"Failed to create SQ for Clock Queue.\");\n", "prefixes": [ "RFC", "11/21" ] }