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GET /api/patches/97002/?format=api
{ "id": 97002, "url": "http://patchwork.dpdk.org/api/patches/97002/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210817134441.1966618-13-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210817134441.1966618-13-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210817134441.1966618-13-michaelba@nvidia.com", "date": "2021-08-17T13:44:32", "name": "[RFC,12/21] common/mlx5: add ROCE disable in context device creation", "commit_ref": null, "pull_url": null, "state": "rfc", "archived": true, "hash": "507303c0dc866916061938060854ffb5b685a0bc", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210817134441.1966618-13-michaelba@nvidia.com/mbox/", "series": [ { "id": 18314, "url": "http://patchwork.dpdk.org/api/series/18314/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18314", "date": "2021-08-17T13:44:20", "name": "mlx5: sharing global MR cache between drivers", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18314/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/97002/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/97002/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D78E0A0548;\n\tTue, 17 Aug 2021 15:46:58 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1390A41210;\n\tTue, 17 Aug 2021 15:45:39 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2067.outbound.protection.outlook.com [40.107.236.67])\n by mails.dpdk.org (Postfix) with ESMTP id D3C46411FD\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Tue, 17 Aug 2021 16:44:32 +0300", "Message-ID": "<20210817134441.1966618-13-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210817134441.1966618-1-michaelba@nvidia.com>", "References": "<20210817134441.1966618-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n DRHQMAIL107.nvidia.com (10.27.9.16)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e2caf681-6833-40de-37e9-08d961854a32", "X-MS-TrafficTypeDiagnostic": "CY4PR1201MB2535:", "X-Microsoft-Antispam-PRVS": "\n <CY4PR1201MB25353840FF94859B6488647DCCFE9@CY4PR1201MB2535.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2201;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n H83G5SpaWPbWyapieaew36/gLaoCEGs13QvzCZB/rH/SrET8mFhajBqfxA3VV+N2sB0DvkrugrLq87rBfJd3AQAiqJ8Tnsq81pD1ldmR0vVKm8FSmBVaXv0Djqp9R1EFHKazn0UFJNKxKKasWZJulqy+wUdDsJKr18mzZ29B9iBc1v82mvzccODe1DKUWuHuKH7g5e2uWyIihIOpy0pZYI6VlKmEyomwERrmCjQT/fHpYGiicSPoJA9euf51yIv6rlznvTdRvxLUzMPDcY7ghdszO6/SSh79pzc3iOOGUOVyggUaPdrunBNnVPoWp63SeFaGmkM6uTleL/Nlt/s1dsh17dHJHsmz2JxBtJ62T6xpL/jzFaZJZdXKIEPYbPhrsI3qfNa10idV6hhQc9GImilQu4N8o4EFJQtiisQzpib4+xVCmJPJ8hv2bgAPLyrbXk7iNjMFAnYAZstgmC1V9hLIAQQ/fNjWwFZNApeAIdc0XqAzzd+OIPZh7+g287Lko5emd0GPylffoWsN6hT4is9MnvxZQuuuSod2gZmk5/QDQ82YrzQOR0Vo9Flr8H7jJfdzU7hXSu7GYjdwgcazDKgDhmYwpIC02dBenKnxvwPIEi3GOyI7VnYVImiWCyne+ulePtw3yoDLHJbW+1m5pxgrx5ot5rE5uIC4JnZotigxtL3UoJWMYLLDkbOBHwSr4JNLqETd+EhUu1Mj5i+Qvg==", "X-Forefront-Antispam-Report": "CIP:216.228.112.32; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid01.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(47076005)(356005)(36756003)(1076003)(26005)(7636003)(83380400001)(8676002)(186003)(86362001)(54906003)(8936002)(16526019)(2906002)(7696005)(2616005)(107886003)(4326008)(82310400003)(36860700001)(6916009)(55016002)(70586007)(70206006)(508600001)(336012)(426003)(6286002)(5660300002)(316002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Aug 2021 13:45:35.1846 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e2caf681-6833-40de-37e9-08d961854a32", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.32];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT023.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR1201MB2535", "Subject": "[dpdk-dev] [RFC 12/21] common/mlx5: add ROCE disable in context\n device creation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add option to get IB device after disabling RoCE. It is relevant if\nthere is vDPA class in device arguments list.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/common/mlx5/linux/mlx5_common_os.c | 126 ++++++++++++++++++++-\n 1 file changed, 125 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/linux/mlx5_common_os.c b/drivers/common/mlx5/linux/mlx5_common_os.c\nindex 6f78897390..4a94865241 100644\n--- a/drivers/common/mlx5/linux/mlx5_common_os.c\n+++ b/drivers/common/mlx5/linux/mlx5_common_os.c\n@@ -15,6 +15,7 @@\n #include <rte_string_fns.h>\n \n #include \"mlx5_common.h\"\n+#include \"mlx5_nl.h\"\n #include \"mlx5_common_log.h\"\n #include \"mlx5_common_os.h\"\n #include \"mlx5_glue.h\"\n@@ -39,6 +40,9 @@ const struct mlx5_glue *mlx5_glue;\n #define MLX5_TXDB_NCACHED 1\n #define MLX5_TXDB_HEURISTIC 2\n \n+#define MLX5_VDPA_MAX_RETRIES 20\n+#define MLX5_VDPA_USEC 1000\n+\n int\n mlx5_get_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr)\n {\n@@ -417,6 +421,123 @@ mlx5_glue_constructor(void)\n \tmlx5_glue = NULL;\n }\n \n+/* Try to disable ROCE by Netlink\\Devlink. */\n+static int\n+mlx5_nl_roce_disable(const char *addr)\n+{\n+\tint nlsk_fd = mlx5_nl_init(NETLINK_GENERIC);\n+\tint devlink_id;\n+\tint enable;\n+\tint ret;\n+\n+\tif (nlsk_fd < 0)\n+\t\treturn nlsk_fd;\n+\tdevlink_id = mlx5_nl_devlink_family_id_get(nlsk_fd);\n+\tif (devlink_id < 0) {\n+\t\tret = devlink_id;\n+\t\tDRV_LOG(DEBUG,\n+\t\t\t\"Failed to get devlink id for ROCE operations by Netlink.\");\n+\t\tgoto close;\n+\t}\n+\tret = mlx5_nl_enable_roce_get(nlsk_fd, devlink_id, addr, &enable);\n+\tif (ret) {\n+\t\tDRV_LOG(DEBUG, \"Failed to get ROCE enable by Netlink: %d.\",\n+\t\t\tret);\n+\t\tgoto close;\n+\t} else if (!enable) {\n+\t\tDRV_LOG(INFO, \"ROCE has already disabled(Netlink).\");\n+\t\tgoto close;\n+\t}\n+\tret = mlx5_nl_enable_roce_set(nlsk_fd, devlink_id, addr, 0);\n+\tif (ret)\n+\t\tDRV_LOG(DEBUG, \"Failed to disable ROCE by Netlink: %d.\", ret);\n+\telse\n+\t\tDRV_LOG(INFO, \"ROCE is disabled by Netlink successfully.\");\n+close:\n+\tclose(nlsk_fd);\n+\treturn ret;\n+}\n+\n+/* Try to disable ROCE by sysfs. */\n+static int\n+mlx5_sys_roce_disable(const char *addr)\n+{\n+\tFILE *file_o;\n+\tint enable;\n+\tint ret;\n+\n+\tMKSTR(file_p, \"/sys/bus/pci/devices/%s/roce_enable\", addr);\n+\tfile_o = fopen(file_p, \"rb\");\n+\tif (!file_o) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -ENOTSUP;\n+\t}\n+\tret = fscanf(file_o, \"%d\", &enable);\n+\tif (ret != 1) {\n+\t\trte_errno = EINVAL;\n+\t\tret = EINVAL;\n+\t\tgoto close;\n+\t} else if (!enable) {\n+\t\tret = 0;\n+\t\tDRV_LOG(INFO, \"ROCE has already disabled(sysfs).\");\n+\t\tgoto close;\n+\t}\n+\tfclose(file_o);\n+\tfile_o = fopen(file_p, \"wb\");\n+\tif (!file_o) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -ENOTSUP;\n+\t}\n+\tfprintf(file_o, \"0\\n\");\n+\tret = 0;\n+close:\n+\tif (ret)\n+\t\tDRV_LOG(DEBUG, \"Failed to disable ROCE by sysfs: %d.\", ret);\n+\telse\n+\t\tDRV_LOG(INFO, \"ROCE is disabled by sysfs successfully.\");\n+\tfclose(file_o);\n+\treturn ret;\n+}\n+\n+static int\n+mlx5_roce_disable(struct rte_device *dev)\n+{\n+\tchar pci_addr[PCI_PRI_STR_SIZE] = { 0 };\n+\n+\tif (mlx5_dev_to_pci_str(dev, pci_addr, sizeof(pci_addr)) < 0)\n+\t\treturn -rte_errno;\n+\t/* Firstly try to disable ROCE by Netlink and fallback to sysfs. */\n+\tif (mlx5_nl_roce_disable(pci_addr) != 0 &&\n+\t mlx5_sys_roce_disable(pci_addr) != 0)\n+\t\treturn -rte_errno;\n+\treturn 0;\n+}\n+\n+static struct ibv_device *\n+mlx5_vdpa_get_ibv_dev(struct rte_device *dev)\n+{\n+\tstruct ibv_device *ibv;\n+\tint retry;\n+\n+\tif (mlx5_roce_disable(dev) != 0) {\n+\t\tDRV_LOG(WARNING, \"Failed to disable ROCE for \\\"%s\\\".\",\n+\t\t\tdev->name);\n+\t\treturn NULL;\n+\t}\n+\t/* Wait for the IB device to appear again after reload. */\n+\tfor (retry = MLX5_VDPA_MAX_RETRIES; retry > 0; --retry) {\n+\t\tibv = mlx5_os_get_ibv_dev(dev);\n+\t\tif (ibv != NULL)\n+\t\t\treturn ibv;\n+\t\tusleep(MLX5_VDPA_USEC);\n+\t}\n+\tDRV_LOG(ERR,\n+\t\t\"Cannot get IB device after disabling RoCE for \\\"%s\\\", retries exceed %d.\",\n+\t\tdev->name, MLX5_VDPA_MAX_RETRIES);\n+\trte_errno = EAGAIN;\n+\treturn NULL;\n+}\n+\n static int\n mlx5_config_doorbell_mapping_env(int dbnc)\n {\n@@ -471,7 +592,10 @@ mlx5_os_devx_open_device(struct mlx5_dev_ctx *dev_ctx, struct rte_device *dev,\n \tstruct ibv_context *ctx = NULL;\n \tint dbmap_env;\n \n-\tibv = mlx5_os_get_ibv_dev(dev);\n+\tif (classes & MLX5_CLASS_VDPA)\n+\t\tibv = mlx5_vdpa_get_ibv_dev(dev);\n+\telse\n+\t\tibv = mlx5_os_get_ibv_dev(dev);\n \tif (!ibv)\n \t\treturn -rte_errno;\n \tDRV_LOG(INFO, \"Dev information matches for device \\\"%s\\\".\", ibv->name);\n", "prefixes": [ "RFC", "12/21" ] }