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GET /api/patches/97009/?format=api
{ "id": 97009, "url": "http://patchwork.dpdk.org/api/patches/97009/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210817134441.1966618-18-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210817134441.1966618-18-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210817134441.1966618-18-michaelba@nvidia.com", "date": "2021-08-17T13:44:37", "name": "[RFC,17/21] regex/mlx5: use HCA attributes from context device", "commit_ref": null, "pull_url": null, "state": "rfc", "archived": true, "hash": "978cc32e3154190216b0a482960e4c7f2ddf1c33", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210817134441.1966618-18-michaelba@nvidia.com/mbox/", "series": [ { "id": 18314, "url": "http://patchwork.dpdk.org/api/series/18314/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18314", "date": "2021-08-17T13:44:20", "name": "mlx5: sharing global MR cache between drivers", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18314/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/97009/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/97009/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B4E98A0548;\n\tTue, 17 Aug 2021 15:47:50 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 734454128F;\n\tTue, 17 Aug 2021 15:45:49 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2041.outbound.protection.outlook.com [40.107.94.41])\n by mails.dpdk.org (Postfix) with ESMTP id A2FF54127F\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Tue, 17 Aug 2021 16:44:37 +0300", "Message-ID": "<20210817134441.1966618-18-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210817134441.1966618-1-michaelba@nvidia.com>", "References": "<20210817134441.1966618-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n DRHQMAIL107.nvidia.com (10.27.9.16)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "3c4e1b45-7a22-4b68-d891-08d96185506c", "X-MS-TrafficTypeDiagnostic": "BN6PR12MB1268:", "X-Microsoft-Antispam-PRVS": "\n <BN6PR12MB126848554D1B8D1DF9316FF4CCFE9@BN6PR12MB1268.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8273;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n o6Y7y4QeYunhzU+5MxYHWX9xj27dnSyYO50jokSdNVHaStdJwHhn+3RyOFxD8l4YwBm4b59clD46vya2GNznqOmz8H/etyaG+2JwPAwu8XajdjmeqsKNhLf4zYIjAfAtN02Gv1xbTLn4duWalmKygRLulSDGy82WJGWL2mwz8f3JrVMtxJ/nv0K+aF0LDVkn6a5YxYX4dGXzJlKsMXJubddUlSKDTa2Mrhd3H7u+xLLB6Nx27ft0nXA2VdqB7VMUTC9vhAa2MrNDP9uScKdWuiltcLPkw98hzCB5o97fW/pGTWceWv83vJoU7DUUs9PUttTegyawHWPF8uNdMCg2UQK9J7HdcX7rQMasPAMupHMDDM7e8nNperIKt/cxLw0mrto0uBfTQ67CPR8Bg2IdgREenXWuxXERe0aCWXSCbcggTIQDIb/WZBRrqTy7s1H8I3lzBQ6Tr0KyQsMdIcephxJQpW7Yl/3WGtbk48fzw8szwsx1EleqINjO89vcxHWVVKw/mT8hfC6xOqDED2rQg/f0Sr76ro+yzHkwtjaWB9X8j1DT80zchosdcAq5JKBjzjmzGLKSHl5C5dy3hMFrbkNp7ce0ldkiJRyZdRuiKLpC8Hv3AY65F06XaW24+PdqQ3oIO07EflNGx8nW+D2yyjCGwK52oEmfl5uXNAnC6HHpP1Yv2rLARoCoD0ef4g4ANM1j5kN6yHY3h0zTt8sSfA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(376002)(39860400002)(346002)(396003)(46966006)(36840700001)(1076003)(82740400003)(16526019)(36860700001)(26005)(478600001)(5660300002)(7696005)(55016002)(36756003)(47076005)(2906002)(70586007)(70206006)(186003)(83380400001)(54906003)(4326008)(316002)(8676002)(336012)(6286002)(86362001)(107886003)(6916009)(82310400003)(6666004)(356005)(7636003)(2616005)(426003)(8936002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Aug 2021 13:45:45.5872 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3c4e1b45-7a22-4b68-d891-08d96185506c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT033.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN6PR12MB1268", "Subject": "[dpdk-dev] [RFC 17/21] regex/mlx5: use HCA attributes from context\n device", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Use HCA attributes from context device structure, instead of query it\nfor itself.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/regex/mlx5/mlx5_regex.c | 18 +++---------------\n 1 file changed, 3 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex 3772007d24..ed3cd8972e 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -126,24 +126,12 @@ mlx5_regex_dev_probe(struct mlx5_common_device *mlx5_dev)\n {\n \tstruct mlx5_regex_priv *priv = NULL;\n \tstruct mlx5_dev_ctx *dev_ctx = &mlx5_dev->ctx;\n-\tstruct mlx5_hca_attr attr;\n \tchar name[RTE_REGEXDEV_NAME_MAX_LEN];\n \tconst char *ibdev_name = mlx5_os_get_ctx_device_name(dev_ctx->ctx);\n \tint ret;\n \tuint32_t val;\n \n \tDRV_LOG(INFO, \"Probe device \\\"%s\\\".\", ibdev_name);\n-\tret = mlx5_devx_cmd_query_hca_attr(dev_ctx->ctx, &attr);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"Unable to read HCA capabilities.\");\n-\t\trte_errno = ENOTSUP;\n-\t\treturn -rte_errno;\n-\t} else if (!attr.regex || attr.regexp_num_of_engines == 0) {\n-\t\tDRV_LOG(ERR, \"Not enough capabilities to support RegEx, maybe \"\n-\t\t\t\"old FW/OFED version?\");\n-\t\trte_errno = ENOTSUP;\n-\t\treturn -rte_errno;\n-\t}\n \tif (mlx5_regex_engines_status(dev_ctx->ctx, 2)) {\n \t\tDRV_LOG(ERR, \"RegEx engine error.\");\n \t\trte_errno = ENOMEM;\n@@ -156,7 +144,7 @@ mlx5_regex_dev_probe(struct mlx5_common_device *mlx5_dev)\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n-\tpriv->sq_ts_format = attr.sq_ts_format;\n+\tpriv->sq_ts_format = dev_ctx->hca_attr.sq_ts_format;\n \tpriv->dev_ctx = dev_ctx;\n \tpriv->nb_engines = 2; /* attr.regexp_num_of_engines */\n \tret = mlx5_devx_regex_register_read(priv->dev_ctx->ctx, 0,\n@@ -190,8 +178,8 @@ mlx5_regex_dev_probe(struct mlx5_common_device *mlx5_dev)\n \tpriv->regexdev->dev_ops = &mlx5_regexdev_ops;\n \tpriv->regexdev->enqueue = mlx5_regexdev_enqueue;\n #ifdef HAVE_MLX5_UMR_IMKEY\n-\tif (!attr.umr_indirect_mkey_disabled &&\n-\t !attr.umr_modify_entity_size_disabled)\n+\tif (!dev_ctx->hca_attr.umr_indirect_mkey_disabled &&\n+\t !dev_ctx->hca_attr.umr_modify_entity_size_disabled)\n \t\tpriv->has_umr = 1;\n \tif (priv->has_umr)\n \t\tpriv->regexdev->enqueue = mlx5_regexdev_enqueue_gga;\n", "prefixes": [ "RFC", "17/21" ] }