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GET /api/patches/97060/?format=api
{ "id": 97060, "url": "http://patchwork.dpdk.org/api/patches/97060/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210818151441.12400-2-rzidane@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210818151441.12400-2-rzidane@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210818151441.12400-2-rzidane@nvidia.com", "date": "2021-08-18T15:14:39", "name": "[RFC,1/3] common/mlx5: add common qp_create", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "61fe83344bf199b95eb51a160be7ddb5c897a681", "submitter": { "id": 2300, "url": "http://patchwork.dpdk.org/api/people/2300/?format=api", "name": "Raja Zidane", "email": "rzidane@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210818151441.12400-2-rzidane@nvidia.com/mbox/", "series": [ { "id": 18334, "url": "http://patchwork.dpdk.org/api/series/18334/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18334", "date": "2021-08-18T15:14:38", "name": "mlx5: replaced hardware queue object", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18334/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/97060/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/97060/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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VsjW9opRUvus5EJhIDlz6ElVzPZ9VmIXlhXkt9KBJTZDBYpUHxB+6kdYcLu+9pkV7o448txNw88mfQNfmuNsKTvku+4SVuQf4vgqVSkkW96j+ZYq5atnjkhNmVrhkw9c7XdrcfUzOOa9lw9CrqvfYGhKlvzLGXdTVFvHNAHbqqecqEoAXV8sdMufVckMhQDCf7i7c7W0GkRSYfA2VEV4rj3NVxaCfTk9tYnwBG4WKxguDYYH7JF7W+Acs5ee+XlQNmjxv2ME15cHxb1rGlqhByvF7xgE5uY1vOKRBJ1IT2FLzsuY+lEh71GHpk+XZrO3g7THrCUVvwMsTMaI2mDyvwzaftyIzCI8mtxfYCB9ZtxGiojc0qT3JkRsu1BkR3X2Y2r8NZQwyhpvRzH5wKBX8mQQzfvwQFrNZb8hGb87hpTDKtjn69MJpIz/qmGVD4waMl5SZb2lXs/9EfTW0oEPAHq8UpAamnRnlPS2vsiybg3twDbL59RRaF1eDLLPu+vax4gW6jJ5kqEABR+kdNSeCibAvENcqOGZ7ClVeh5vNU3u11EF6vP4z1etqWMBoPJtKZd3aIN/xnnGcGvWsz2Vf0APErvkgtosl8V2eZ941s+1YNRcndmE9kTfUVjI9q15dgYKP6N2IRMvLuHtyx+4XaU644R91WWUpvJqPW9W4NOcCrhKWigftGkiXdazjOqEQ7ewMls1WyTFGBOZSrAlOQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(396003)(39860400002)(346002)(376002)(36840700001)(46966006)(336012)(30864003)(36860700001)(82310400003)(70586007)(70206006)(1076003)(86362001)(6666004)(426003)(5660300002)(83380400001)(47076005)(2906002)(7696005)(36756003)(8936002)(2616005)(107886003)(4326008)(8676002)(55016002)(26005)(7636003)(16526019)(356005)(478600001)(6916009)(186003)(6286002)(54906003)(316002)(82740400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Aug 2021 15:15:09.5362 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n bd417a19-dba8-4924-1eb9-08d9625af800", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT067.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4242", "Subject": "[dpdk-dev] [RFC 1/3] common/mlx5: add common qp_create", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Raja Zidane <rzidane@nvidia.com>\n---\n drivers/common/mlx5/mlx5_common_devx.c | 111 +++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_common_devx.h | 20 +++++\n drivers/common/mlx5/version.map | 2 +\n drivers/crypto/mlx5/mlx5_crypto.c | 80 +++++++-----------\n drivers/crypto/mlx5/mlx5_crypto.h | 5 +-\n drivers/vdpa/mlx5/mlx5_vdpa.h | 5 +-\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 58 ++++---------\n 7 files changed, 181 insertions(+), 100 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c\nindex 22c8d356c4..640fe3bbb9 100644\n--- a/drivers/common/mlx5/mlx5_common_devx.c\n+++ b/drivers/common/mlx5/mlx5_common_devx.c\n@@ -271,6 +271,117 @@ mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj, uint16_t log_wqbb_n,\n \treturn -rte_errno;\n }\n \n+/**\n+ * Destroy DevX Queue Pair.\n+ *\n+ * @param[in] qp\n+ * DevX QP to destroy.\n+ */\n+void\n+mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp)\n+{\n+\tif (qp->qp)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(qp->qp));\n+\tif (qp->umem_obj)\n+\t\tclaim_zero(mlx5_os_umem_dereg(qp->umem_obj));\n+\tif (qp->umem_buf)\n+\t\tmlx5_free((void *)(uintptr_t)qp->umem_buf);\n+}\n+\n+/**\n+ * Create Queue Pair using DevX API.\n+ *\n+ * Get a pointer to partially initialized attributes structure, and updates the\n+ * following fields:\n+ * wq_umem_id\n+ * wq_umem_offset\n+ * dbr_umem_valid\n+ * dbr_umem_id\n+ * dbr_address\n+ * sq_size\n+ * log_page_size\n+ *\t rq_size\n+ * All other fields are updated by caller.\n+ *\n+ * @param[in] ctx\n+ * Context returned from mlx5 open_device() glue function.\n+ * @param[in/out] qp_obj\n+ * Pointer to QP to create.\n+ * @param[in] log_wqbb_n\n+ * Log of number of WQBBs in queue.\n+ * @param[in] attr\n+ * Pointer to QP attributes structure.\n+ * @param[in] socket\n+ * Socket to use for allocation.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint16_t log_wqbb_n,\n+\t\t struct mlx5_devx_qp_attr *attr, int socket)\n+{\n+\tstruct mlx5_devx_obj *qp = NULL;\n+\tstruct mlx5dv_devx_umem *umem_obj = NULL;\n+\tvoid *umem_buf = NULL;\n+\tsize_t alignment = MLX5_WQE_BUF_ALIGNMENT;\n+\tuint32_t umem_size, umem_dbrec;\n+\tuint16_t qp_size = 1 << log_wqbb_n;\n+\tint ret;\n+\n+\tif (alignment == (size_t)-1) {\n+\t\tDRV_LOG(ERR, \"Failed to get WQE buf alignment.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\t/* Allocate memory buffer for WQEs and doorbell record. */\n+\tumem_size = MLX5_WQE_SIZE * qp_size;\n+\tumem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);\n+\tumem_size += MLX5_DBR_SIZE;\n+\tumem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,\n+\t\t\t alignment, socket);\n+\tif (!umem_buf) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate memory for QP.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\t/* Register allocated buffer in user space with DevX. */\n+\tumem_obj = mlx5_os_umem_reg(ctx, (void *)(uintptr_t)umem_buf, umem_size,\n+\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n+\tif (!umem_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to register umem for QP.\");\n+\t\trte_errno = errno;\n+\t\tgoto error;\n+\t}\n+\t/* Fill attributes for SQ object creation. */\n+\tattr->wq_umem_id = mlx5_os_get_umem_id(umem_obj);\n+\tattr->wq_umem_offset = 0;\n+\tattr->dbr_umem_valid = 1;\n+\tattr->dbr_umem_id = attr->wq_umem_id;\n+\tattr->dbr_address = umem_dbrec;\n+\tattr->log_page_size = MLX5_LOG_PAGE_SIZE;\n+\t/* Create send queue object with DevX. */\n+\tqp = mlx5_devx_cmd_create_qp(ctx, attr);\n+\tif (!qp) {\n+\t\tDRV_LOG(ERR, \"Can't create DevX QP object.\");\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tqp_obj->umem_buf = umem_buf;\n+\tqp_obj->umem_obj = umem_obj;\n+\tqp_obj->qp = qp;\n+\tqp_obj->db_rec = RTE_PTR_ADD(qp_obj->umem_buf, umem_dbrec);\n+\treturn 0;\n+error:\n+\tret = rte_errno;\n+\tif (umem_obj)\n+\t\tclaim_zero(mlx5_os_umem_dereg(umem_obj));\n+\tif (umem_buf)\n+\t\tmlx5_free((void *)(uintptr_t)umem_buf);\n+\trte_errno = ret;\n+\treturn -rte_errno;\n+}\n+\n /**\n * Destroy DevX Receive Queue.\n *\ndiff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h\nindex aad0184e5a..b05260b401 100644\n--- a/drivers/common/mlx5/mlx5_common_devx.h\n+++ b/drivers/common/mlx5/mlx5_common_devx.h\n@@ -33,6 +33,18 @@ struct mlx5_devx_sq {\n \tvolatile uint32_t *db_rec; /* The SQ doorbell record. */\n };\n \n+/* DevX Queue Pair structure. */\n+struct mlx5_devx_qp {\n+\tstruct mlx5_devx_obj *qp; /* The QP DevX object. */\n+\tvoid *umem_obj; /* The QP umem object. */\n+\tunion {\n+\t\tvoid *umem_buf;\n+\t\tstruct mlx5_wqe *wqes; /* The QP ring buffer. */\n+\t\tstruct mlx5_aso_wqe *aso_wqes;\n+\t};\n+\tvolatile uint32_t *db_rec; /* The QP doorbell record. */\n+};\n+\n /* DevX Receive Queue structure. */\n struct mlx5_devx_rq {\n \tstruct mlx5_devx_obj *rq; /* The RQ DevX object. */\n@@ -59,6 +71,14 @@ int mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj,\n \t\t\tuint16_t log_wqbb_n,\n \t\t\tstruct mlx5_devx_create_sq_attr *attr, int socket);\n \n+__rte_internal\n+void mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp);\n+\n+__rte_internal\n+int mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj,\n+\t\t\tuint16_t log_wqbb_n,\n+\t\t\tstruct mlx5_devx_qp_attr *attr, int socket);\n+\n __rte_internal\n void mlx5_devx_rq_destroy(struct mlx5_devx_rq *rq);\n \ndiff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map\nindex e5cb6b7060..9487f787b6 100644\n--- a/drivers/common/mlx5/version.map\n+++ b/drivers/common/mlx5/version.map\n@@ -71,6 +71,8 @@ INTERNAL {\n \tmlx5_devx_rq_destroy;\n \tmlx5_devx_sq_create;\n \tmlx5_devx_sq_destroy;\n+\tmlx5_devx_qp_create;\n+\tmlx5_devx_qp_destroy;\n \n \tmlx5_free;\n \ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex b3d5200ca3..c66a3a7add 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -257,12 +257,12 @@ mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n {\n \tstruct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];\n \n-\tif (qp->qp_obj != NULL)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(qp->qp_obj));\n-\tif (qp->umem_obj != NULL)\n-\t\tclaim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj));\n-\tif (qp->umem_buf != NULL)\n-\t\trte_free(qp->umem_buf);\n+\tif (qp->qp_obj.qp != NULL)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(qp->qp_obj.qp));\n+\tif (qp->qp_obj.umem_obj != NULL)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(qp->qp_obj.umem_obj));\n+\tif (qp->qp_obj.umem_buf != NULL)\n+\t\trte_free(qp->qp_obj.umem_buf);\n \tmlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);\n \tmlx5_devx_cq_destroy(&qp->cq_obj);\n \trte_free(qp);\n@@ -277,20 +277,20 @@ mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp)\n \t * In Order to configure self loopback, when calling these functions the\n \t * remote QP id that is used is the id of the same QP.\n \t */\n-\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RST2INIT_QP,\n-\t\t\t\t\t qp->qp_obj->id)) {\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj.qp, MLX5_CMD_OP_RST2INIT_QP,\n+\t\t\t\t\t qp->qp_obj.qp->id)) {\n \t\tDRV_LOG(ERR, \"Failed to modify QP to INIT state(%u).\",\n \t\t\trte_errno);\n \t\treturn -1;\n \t}\n-\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_INIT2RTR_QP,\n-\t\t\t\t\t qp->qp_obj->id)) {\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj.qp, MLX5_CMD_OP_INIT2RTR_QP,\n+\t\t\t\t\t qp->qp_obj.qp->id)) {\n \t\tDRV_LOG(ERR, \"Failed to modify QP to RTR state(%u).\",\n \t\t\trte_errno);\n \t\treturn -1;\n \t}\n-\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RTR2RTS_QP,\n-\t\t\t\t\t qp->qp_obj->id)) {\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp_obj.qp, MLX5_CMD_OP_RTR2RTS_QP,\n+\t\t\t\t\t qp->qp_obj.qp->id)) {\n \t\tDRV_LOG(ERR, \"Failed to modify QP to RTS state(%u).\",\n \t\t\trte_errno);\n \t\treturn -1;\n@@ -452,7 +452,7 @@ mlx5_crypto_wqe_set(struct mlx5_crypto_priv *priv,\n \t\tmemcpy(klms, &umr->kseg[0], sizeof(*klms) * klm_n);\n \t}\n \tds = 2 + klm_n;\n-\tcseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | ds);\n+\tcseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | ds);\n \tcseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) |\n \t\t\t\t\t\t\tMLX5_OPCODE_RDMA_WRITE);\n \tds = RTE_ALIGN(ds, 4);\n@@ -461,7 +461,7 @@ mlx5_crypto_wqe_set(struct mlx5_crypto_priv *priv,\n \tif (priv->max_rdmar_ds > ds) {\n \t\tcseg += ds;\n \t\tds = priv->max_rdmar_ds - ds;\n-\t\tcseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | ds);\n+\t\tcseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | ds);\n \t\tcseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) |\n \t\t\t\t\t\t\t MLX5_OPCODE_NOP);\n \t\tqp->db_pi += ds >> 2; /* Here, DS is 4 aligned for sure. */\n@@ -503,7 +503,7 @@ mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,\n \t\treturn 0;\n \tdo {\n \t\top = *ops++;\n-\t\tumr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * qp->pi);\n+\t\tumr = RTE_PTR_ADD(qp->qp_obj.umem_buf, priv->wqe_set_size * qp->pi);\n \t\tif (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0)) {\n \t\t\tqp->stats.enqueue_err_count++;\n \t\t\tif (remain != nb_ops) {\n@@ -517,7 +517,7 @@ mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,\n \t} while (--remain);\n \tqp->stats.enqueued_count += nb_ops;\n \trte_io_wmb();\n-\tqp->db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi);\n+\tqp->qp_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi);\n \trte_wmb();\n \tmlx5_crypto_uar_write(*(volatile uint64_t *)qp->wqe, qp->priv);\n \trte_wmb();\n@@ -583,7 +583,7 @@ mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp)\n \tuint32_t i;\n \n \tfor (i = 0 ; i < qp->entries_n; i++) {\n-\t\tstruct mlx5_wqe_cseg *cseg = RTE_PTR_ADD(qp->umem_buf, i *\n+\t\tstruct mlx5_wqe_cseg *cseg = RTE_PTR_ADD(qp->qp_obj.umem_buf, i *\n \t\t\t\t\t\t\t priv->wqe_set_size);\n \t\tstruct mlx5_wqe_umr_cseg *ucseg = (struct mlx5_wqe_umr_cseg *)\n \t\t\t\t\t\t\t\t (cseg + 1);\n@@ -593,7 +593,7 @@ mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp)\n \t\tstruct mlx5_wqe_rseg *rseg;\n \n \t\t/* Init UMR WQE. */\n-\t\tcseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) |\n+\t\tcseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) |\n \t\t\t\t\t (priv->umr_wqe_size / MLX5_WSEG_SIZE));\n \t\tcseg->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<\n \t\t\t\t MLX5_COMP_MODE_OFFSET);\n@@ -628,7 +628,7 @@ mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,\n \t\t.klm_num = RTE_ALIGN(priv->max_segs_num, 4),\n \t};\n \n-\tfor (umr = (struct mlx5_umr_wqe *)qp->umem_buf, i = 0;\n+\tfor (umr = (struct mlx5_umr_wqe *)qp->qp_obj.umem_buf, i = 0;\n \t i < qp->entries_n; i++, umr = RTE_PTR_ADD(umr, priv->wqe_set_size)) {\n \t\tattr.klm_array = (struct mlx5_klm *)&umr->kseg[0];\n \t\tqp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->ctx, &attr);\n@@ -649,9 +649,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tstruct mlx5_devx_qp_attr attr = {0};\n \tstruct mlx5_crypto_qp *qp;\n \tuint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors);\n-\tuint32_t umem_size = RTE_BIT32(log_nb_desc) *\n-\t\t\t priv->wqe_set_size +\n-\t\t\t sizeof(*qp->db_rec) * 2;\n+\tuint32_t ret;\n \tuint32_t alloc_size = sizeof(*qp);\n \tstruct mlx5_devx_cq_attr cq_attr = {\n \t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),\n@@ -675,18 +673,15 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto error;\n \t}\n-\tqp->umem_buf = rte_zmalloc_socket(__func__, umem_size, 4096, socket_id);\n-\tif (qp->umem_buf == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate QP umem.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\tqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n-\t\t\t\t\t (void *)(uintptr_t)qp->umem_buf,\n-\t\t\t\t\t umem_size,\n-\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n-\tif (qp->umem_obj == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to register QP umem.\");\n+\t/* fill attributes*/\n+\tattr.pd = priv->pdn;\n+\tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);\n+\tattr.cqn = qp->cq_obj.cq->id;\n+\tattr.rq_size = 0;\n+\tattr.sq_size = RTE_BIT32(log_nb_desc);\n+\tret = mlx5_devx_qp_create(priv->ctx, &qp->qp_obj, log_nb_desc, &attr, socket_id);\n+\tif(ret) {\n+\t\tDRV_LOG(ERR, \"Failed to create QP\");\n \t\tgoto error;\n \t}\n \tif (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,\n@@ -697,23 +692,6 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\tgoto error;\n \t}\n \tqp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;\n-\tattr.pd = priv->pdn;\n-\tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);\n-\tattr.cqn = qp->cq_obj.cq->id;\n-\tattr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));\n-\tattr.rq_size = 0;\n-\tattr.sq_size = RTE_BIT32(log_nb_desc);\n-\tattr.dbr_umem_valid = 1;\n-\tattr.wq_umem_id = qp->umem_obj->umem_id;\n-\tattr.wq_umem_offset = 0;\n-\tattr.dbr_umem_id = qp->umem_obj->umem_id;\n-\tattr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size;\n-\tqp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n-\tif (qp->qp_obj == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to create QP(%u).\", rte_errno);\n-\t\tgoto error;\n-\t}\n-\tqp->db_rec = RTE_PTR_ADD(qp->umem_buf, (uintptr_t)attr.dbr_address);\n \tif (mlx5_crypto_qp2rts(qp))\n \t\tgoto error;\n \tqp->mkey = (struct mlx5_devx_obj **)RTE_ALIGN((uintptr_t)(qp + 1),\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex d49b0001f0..013eed30b5 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -43,11 +43,8 @@ struct mlx5_crypto_priv {\n struct mlx5_crypto_qp {\n \tstruct mlx5_crypto_priv *priv;\n \tstruct mlx5_devx_cq cq_obj;\n-\tstruct mlx5_devx_obj *qp_obj;\n+\tstruct mlx5_devx_qp qp_obj;\n \tstruct rte_cryptodev_stats stats;\n-\tstruct mlx5dv_devx_umem *umem_obj;\n-\tvoid *umem_buf;\n-\tvolatile uint32_t *db_rec;\n \tstruct rte_crypto_op **ops;\n \tstruct mlx5_devx_obj **mkey; /* WQE's indirect mekys. */\n \tstruct mlx5_mr_ctrl mr_ctrl;\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h\nindex 2a04e36607..a27f3fdadb 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.h\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h\n@@ -54,10 +54,7 @@ struct mlx5_vdpa_cq {\n struct mlx5_vdpa_event_qp {\n \tstruct mlx5_vdpa_cq cq;\n \tstruct mlx5_devx_obj *fw_qp;\n-\tstruct mlx5_devx_obj *sw_qp;\n-\tstruct mlx5dv_devx_umem *umem_obj;\n-\tvoid *umem_buf;\n-\tvolatile uint32_t *db_rec;\n+\tstruct mlx5_devx_qp sw_qp;\n };\n \n struct mlx5_vdpa_query_mr {\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\nindex 3541c652ce..d327a605fa 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n@@ -179,7 +179,7 @@ mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)\n \t\tcq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n \t\trte_io_wmb();\n \t\t/* Ring SW QP doorbell record. */\n-\t\teqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);\n+\t\teqp->sw_qp.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);\n \t}\n \treturn comp;\n }\n@@ -531,12 +531,12 @@ mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)\n void\n mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)\n {\n-\tif (eqp->sw_qp)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));\n-\tif (eqp->umem_obj)\n-\t\tclaim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));\n-\tif (eqp->umem_buf)\n-\t\trte_free(eqp->umem_buf);\n+\tif (eqp->sw_qp.qp)\n+\t\tclaim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp.qp));\n+\tif (eqp->sw_qp.umem_obj)\n+\t\tclaim_zero(mlx5_glue->devx_umem_dereg(eqp->sw_qp.umem_obj));\n+\tif (eqp->sw_qp.umem_buf)\n+\t\trte_free(eqp->sw_qp.umem_buf);\n \tif (eqp->fw_qp)\n \t\tclaim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));\n \tmlx5_vdpa_cq_destroy(&eqp->cq);\n@@ -547,36 +547,36 @@ static int\n mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)\n {\n \tif (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,\n-\t\t\t\t\t eqp->sw_qp->id)) {\n+\t\t\t\t\t eqp->sw_qp.qp->id)) {\n \t\tDRV_LOG(ERR, \"Failed to modify FW QP to INIT state(%u).\",\n \t\t\trte_errno);\n \t\treturn -1;\n \t}\n-\tif (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,\n+\tif (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp.qp, MLX5_CMD_OP_RST2INIT_QP,\n \t\t\t\t\t eqp->fw_qp->id)) {\n \t\tDRV_LOG(ERR, \"Failed to modify SW QP to INIT state(%u).\",\n \t\t\trte_errno);\n \t\treturn -1;\n \t}\n \tif (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,\n-\t\t\t\t\t eqp->sw_qp->id)) {\n+\t\t\t\t\t eqp->sw_qp.qp->id)) {\n \t\tDRV_LOG(ERR, \"Failed to modify FW QP to RTR state(%u).\",\n \t\t\trte_errno);\n \t\treturn -1;\n \t}\n-\tif (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,\n+\tif (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp.qp, MLX5_CMD_OP_INIT2RTR_QP,\n \t\t\t\t\t eqp->fw_qp->id)) {\n \t\tDRV_LOG(ERR, \"Failed to modify SW QP to RTR state(%u).\",\n \t\t\trte_errno);\n \t\treturn -1;\n \t}\n \tif (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,\n-\t\t\t\t\t eqp->sw_qp->id)) {\n+\t\t\t\t\t eqp->sw_qp.qp->id)) {\n \t\tDRV_LOG(ERR, \"Failed to modify FW QP to RTS state(%u).\",\n \t\t\trte_errno);\n \t\treturn -1;\n \t}\n-\tif (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,\n+\tif (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp.qp, MLX5_CMD_OP_RTR2RTS_QP,\n \t\t\t\t\t eqp->fw_qp->id)) {\n \t\tDRV_LOG(ERR, \"Failed to modify SW QP to RTS state(%u).\",\n \t\t\trte_errno);\n@@ -591,8 +591,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,\n {\n \tstruct mlx5_devx_qp_attr attr = {0};\n \tuint16_t log_desc_n = rte_log2_u32(desc_n);\n-\tuint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +\n-\t\t\t\t\t\t sizeof(*eqp->db_rec) * 2;\n+\tuint32_t ret;\n \n \tif (mlx5_vdpa_event_qp_global_prepare(priv))\n \t\treturn -1;\n@@ -605,42 +604,19 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,\n \t\tDRV_LOG(ERR, \"Failed to create FW QP(%u).\", rte_errno);\n \t\tgoto error;\n \t}\n-\teqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);\n-\tif (!eqp->umem_buf) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate memory for SW QP.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto error;\n-\t}\n-\teqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n-\t\t\t\t\t (void *)(uintptr_t)eqp->umem_buf,\n-\t\t\t\t\t umem_size,\n-\t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n-\tif (!eqp->umem_obj) {\n-\t\tDRV_LOG(ERR, \"Failed to register umem for SW QP.\");\n-\t\tgoto error;\n-\t}\n-\tattr.uar_index = priv->uar->page_id;\n-\tattr.cqn = eqp->cq.cq_obj.cq->id;\n-\tattr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));\n \tattr.rq_size = 1 << log_desc_n;\n \tattr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);\n \tattr.sq_size = 0; /* No need SQ. */\n-\tattr.dbr_umem_valid = 1;\n-\tattr.wq_umem_id = eqp->umem_obj->umem_id;\n-\tattr.wq_umem_offset = 0;\n-\tattr.dbr_umem_id = eqp->umem_obj->umem_id;\n \tattr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format);\n-\tattr.dbr_address = RTE_BIT64(log_desc_n) * MLX5_WSEG_SIZE;\n-\teqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n-\tif (!eqp->sw_qp) {\n+\tret = mlx5_devx_qp_create(priv->ctx, &(eqp->sw_qp), log_desc_n, &attr, SOCKET_ID_ANY);\n+\tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to create SW QP(%u).\", rte_errno);\n \t\tgoto error;\n \t}\n-\teqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);\n \tif (mlx5_vdpa_qps2rts(eqp))\n \t\tgoto error;\n \t/* First ringing. */\n-\trte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);\n+\trte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->sw_qp.db_rec[0]);\n \treturn 0;\n error:\n \tmlx5_vdpa_event_qp_destroy(eqp);\n", "prefixes": [ "RFC", "1/3" ] }