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GET /api/patches/97760/?format=api
{ "id": 97760, "url": "http://patchwork.dpdk.org/api/patches/97760/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210902070034.1086-2-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210902070034.1086-2-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210902070034.1086-2-pbhagavatula@marvell.com", "date": "2021-09-02T07:00:33", "name": "[2/2] event/cnxk: use common XAQ pool APIs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d749b2e42c4781274b5301b3c5726816f4d39ce1", "submitter": { "id": 1183, "url": "http://patchwork.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210902070034.1086-2-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 18614, "url": "http://patchwork.dpdk.org/api/series/18614/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18614", "date": "2021-09-02T07:00:33", "name": "[1/2] common/cnxk: add SSO XAQ pool create and free", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18614/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/97760/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/97760/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 96938A0547;\n\tThu, 2 Sep 2021 09:00:51 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 80B1040142;\n\tThu, 2 Sep 2021 09:00:51 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 63E2C4013F\n for <dev@dpdk.org>; Thu, 2 Sep 2021 09:00:50 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1823lgcu027670\n for <dev@dpdk.org>; Thu, 2 Sep 2021 00:00:49 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 3atdwqae6t-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 02 Sep 2021 00:00:49 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 2 Sep 2021 00:00:47 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 2 Sep 2021 00:00:47 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 31C1E3F7051;\n Thu, 2 Sep 2021 00:00:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=O9iyS2SaeqHlenZa/rEAc7PSbSMy8pFT4aC6U3RLLig=;\n b=VePFWymHNgm5JNw8MtF8UZT7brrqs8Hn/hYR9pxXOxTA3Pjwa2g1XNatUHpkw6PoKcK6\n f/xBY3XdebroSf+en8C/jyZ6PlQQ2Vt+A5a3hzFl1qSGXNOwziUzNLWuQd8nx25W8XXk\n Xxp0N8T4SZuRmzo2uKCHGTkunNfdWtczxJ6GGut8obadNQe6xRU1c0ROZyq8sGtkh1mo\n CPmVVYwza3xrp+SUjHsDh25Bzd7RF0dBDjrtuho2CBa3hVhBGR1fOzJQPzRhk5ZJL6zn\n fx5913D3fD3kUjSK0hO1Fj89mTfYGR1rRwkKIB6JXgRS0cjK2C2ZfUWpQ2rbBTE59KqA yQ==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Thu, 2 Sep 2021 12:30:33 +0530", "Message-ID": "<20210902070034.1086-2-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210902070034.1086-1-pbhagavatula@marvell.com>", "References": "<20210902070034.1086-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "S9OQFb7jNqjSe_p-efrb4293IDoGskqk", "X-Proofpoint-GUID": "S9OQFb7jNqjSe_p-efrb4293IDoGskqk", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-02_02,2021-09-01_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 2/2] event/cnxk: use common XAQ pool APIs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nUse the common APIs to create and fre XAQ pool.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/cnxk/cn10k_eventdev.c | 4 +-\n drivers/event/cnxk/cn9k_eventdev.c | 6 +-\n drivers/event/cnxk/cnxk_eventdev.c | 127 ++++------------------------\n drivers/event/cnxk/cnxk_eventdev.h | 3 -\n 4 files changed, 21 insertions(+), 119 deletions(-)", "diff": "diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex bd1cf55d2c..ed185262d1 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -98,7 +98,7 @@ cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)\n \n \trte_memcpy(ws->grps_base, grps_base,\n \t\t sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);\n-\tws->fc_mem = dev->fc_mem;\n+\tws->fc_mem = (uint64_t *)dev->fc_iova;\n \tws->xaq_lmt = dev->xaq_lmt;\n \n \t/* Set get_work timeout for HWS */\n@@ -467,8 +467,6 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)\n \t\treturn -EINVAL;\n \t}\n \n-\troc_sso_rsrc_fini(&dev->sso);\n-\n \trc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,\n \t\t\t\t dev->nb_event_queues);\n \tif (rc < 0) {\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 0c7206cb96..7a2dbcbe35 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -100,7 +100,7 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)\n \t\tdws = hws;\n \t\trte_memcpy(dws->grps_base, grps_base,\n \t\t\t sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);\n-\t\tdws->fc_mem = dev->fc_mem;\n+\t\tdws->fc_mem = (uint64_t *)dev->fc_iova;\n \t\tdws->xaq_lmt = dev->xaq_lmt;\n \n \t\tplt_write64(val, dws->base[0] + SSOW_LF_GWS_NW_TIM);\n@@ -109,7 +109,7 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)\n \t\tws = hws;\n \t\trte_memcpy(ws->grps_base, grps_base,\n \t\t\t sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);\n-\t\tws->fc_mem = dev->fc_mem;\n+\t\tws->fc_mem = (uint64_t *)dev->fc_iova;\n \t\tws->xaq_lmt = dev->xaq_lmt;\n \n \t\tplt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);\n@@ -728,8 +728,6 @@ cn9k_sso_dev_configure(const struct rte_eventdev *event_dev)\n \t\treturn -EINVAL;\n \t}\n \n-\troc_sso_rsrc_fini(&dev->sso);\n-\n \trc = cn9k_sso_rsrc_init(dev, dev->nb_event_ports, dev->nb_event_queues);\n \tif (rc < 0) {\n \t\tplt_err(\"Failed to initialize SSO resources\");\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex 9a87239a59..84bf8cb6d1 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -125,101 +125,30 @@ cnxk_sso_info_get(struct cnxk_sso_evdev *dev,\n int\n cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev)\n {\n-\tchar pool_name[RTE_MEMZONE_NAMESIZE];\n-\tuint32_t xaq_cnt, npa_aura_id;\n-\tconst struct rte_memzone *mz;\n-\tstruct npa_aura_s *aura;\n-\tstatic int reconfig_cnt;\n+\tuint32_t xae_cnt;\n \tint rc;\n \n-\tif (dev->xaq_pool) {\n-\t\trc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);\n-\t\tif (rc < 0) {\n-\t\t\tplt_err(\"Failed to release XAQ %d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t\trte_mempool_free(dev->xaq_pool);\n-\t\tdev->xaq_pool = NULL;\n-\t}\n-\n-\t/*\n-\t * Allocate memory for Add work backpressure.\n-\t */\n-\tmz = rte_memzone_lookup(CNXK_SSO_FC_NAME);\n-\tif (mz == NULL)\n-\t\tmz = rte_memzone_reserve_aligned(CNXK_SSO_FC_NAME,\n-\t\t\t\t\t\t sizeof(struct npa_aura_s) +\n-\t\t\t\t\t\t\t RTE_CACHE_LINE_SIZE,\n-\t\t\t\t\t\t 0, 0, RTE_CACHE_LINE_SIZE);\n-\tif (mz == NULL) {\n-\t\tplt_err(\"Failed to allocate mem for fcmem\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tdev->fc_iova = mz->iova;\n-\tdev->fc_mem = mz->addr;\n-\n-\taura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem +\n-\t\t\t\t RTE_CACHE_LINE_SIZE);\n-\tmemset(aura, 0, sizeof(struct npa_aura_s));\n-\n-\taura->fc_ena = 1;\n-\taura->fc_addr = dev->fc_iova;\n-\taura->fc_hyst_bits = 0; /* Store count on all updates */\n-\n-\t/* Taken from HRM 14.3.3(4) */\n-\txaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT;\n+\txae_cnt = 0;\n \tif (dev->xae_cnt)\n-\t\txaq_cnt += dev->xae_cnt / dev->sso.xae_waes;\n+\t\txae_cnt += dev->xae_cnt;\n \telse if (dev->adptr_xae_cnt)\n-\t\txaq_cnt += (dev->adptr_xae_cnt / dev->sso.xae_waes) +\n-\t\t\t (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);\n+\t\txae_cnt += (dev->adptr_xae_cnt);\n \telse\n-\t\txaq_cnt += (dev->sso.iue / dev->sso.xae_waes) +\n-\t\t\t (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);\n-\n-\tplt_sso_dbg(\"Configuring %d xaq buffers\", xaq_cnt);\n-\t/* Setup XAQ based on number of nb queues. */\n-\tsnprintf(pool_name, 30, \"cnxk_xaq_buf_pool_%d\", reconfig_cnt);\n-\tdev->xaq_pool = (void *)rte_mempool_create_empty(\n-\t\tpool_name, xaq_cnt, dev->sso.xaq_buf_size, 0, 0,\n-\t\trte_socket_id(), 0);\n-\n-\tif (dev->xaq_pool == NULL) {\n-\t\tplt_err(\"Unable to create empty mempool.\");\n-\t\trte_memzone_free(mz);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\trc = rte_mempool_set_ops_byname(dev->xaq_pool,\n-\t\t\t\t\trte_mbuf_platform_mempool_ops(), aura);\n-\tif (rc != 0) {\n-\t\tplt_err(\"Unable to set xaqpool ops.\");\n-\t\tgoto alloc_fail;\n-\t}\n+\t\txae_cnt += dev->sso.iue;\n \n-\trc = rte_mempool_populate_default(dev->xaq_pool);\n+\tplt_sso_dbg(\"Configuring %d xae buffers\", xae_cnt);\n+\trc = roc_sso_hwgrp_init_xaq_aura(&dev->sso, xae_cnt);\n \tif (rc < 0) {\n-\t\tplt_err(\"Unable to set populate xaqpool.\");\n-\t\tgoto alloc_fail;\n+\t\tplt_err(\"Failed to configure XAQ aura\");\n+\t\treturn rc;\n \t}\n-\treconfig_cnt++;\n-\t/* When SW does addwork (enqueue) check if there is space in XAQ by\n-\t * comparing fc_addr above against the xaq_lmt calculated below.\n-\t * There should be a minimum headroom (CNXK_SSO_XAQ_SLACK / 2) for SSO\n-\t * to request XAQ to cache them even before enqueue is called.\n-\t */\n-\tdev->xaq_lmt =\n-\t\txaq_cnt - (CNXK_SSO_XAQ_SLACK / 2 * dev->nb_event_queues);\n-\tdev->nb_xaq_cfg = xaq_cnt;\n-\n-\tnpa_aura_id = roc_npa_aura_handle_to_aura(dev->xaq_pool->pool_id);\n-\treturn roc_sso_hwgrp_alloc_xaq(&dev->sso, npa_aura_id,\n-\t\t\t\t dev->nb_event_queues);\n-alloc_fail:\n-\trte_mempool_free(dev->xaq_pool);\n-\trte_memzone_free(mz);\n-\treturn rc;\n+\tdev->xaq_lmt = dev->sso.xaq.xaq_lmt;\n+\tdev->fc_iova = (uint64_t)dev->sso.xaq.fc;\n+\n+\treturn roc_sso_hwgrp_alloc_xaq(\n+\t\t&dev->sso,\n+\t\troc_npa_aura_handle_to_aura(dev->sso.xaq.aura_handle),\n+\t\tdev->nb_event_queues);\n }\n \n int\n@@ -231,14 +160,6 @@ cnxk_sso_xae_reconfigure(struct rte_eventdev *event_dev)\n \tif (event_dev->data->dev_started)\n \t\tevent_dev->dev_ops->dev_stop(event_dev);\n \n-\trc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);\n-\tif (rc < 0) {\n-\t\tplt_err(\"Failed to release XAQ %d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\trte_mempool_free(dev->xaq_pool);\n-\tdev->xaq_pool = NULL;\n \trc = cnxk_sso_xaq_allocate(dev);\n \tif (rc < 0) {\n \t\tplt_err(\"Failed to alloc XAQ %d\", rc);\n@@ -320,7 +241,6 @@ cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)\n \tstruct rte_event_dev_config *conf = &event_dev->data->dev_conf;\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tuint32_t deq_tmo_ns;\n-\tint rc;\n \n \tdeq_tmo_ns = conf->dequeue_timeout_ns;\n \n@@ -354,15 +274,8 @@ cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)\n \t\treturn -EINVAL;\n \t}\n \n-\tif (dev->xaq_pool) {\n-\t\trc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);\n-\t\tif (rc < 0) {\n-\t\t\tplt_err(\"Failed to release XAQ %d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t\trte_mempool_free(dev->xaq_pool);\n-\t\tdev->xaq_pool = NULL;\n-\t}\n+\troc_sso_rsrc_fini(&dev->sso);\n+\troc_sso_hwgrp_free_xaq_aura(&dev->sso, dev->sso.nb_hwgrp);\n \n \tdev->nb_event_queues = conf->nb_event_queues;\n \tdev->nb_event_ports = conf->nb_event_ports;\n@@ -556,12 +469,8 @@ cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn)\n \t}\n \n \troc_sso_rsrc_fini(&dev->sso);\n-\trte_mempool_free(dev->xaq_pool);\n-\trte_memzone_free(rte_memzone_lookup(CNXK_SSO_FC_NAME));\n \n \tdev->fc_iova = 0;\n-\tdev->fc_mem = NULL;\n-\tdev->xaq_pool = NULL;\n \tdev->configured = false;\n \tdev->is_timeout_deq = 0;\n \tdev->nb_event_ports = 0;\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 8a5c737e4b..ccd09b1d82 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -91,11 +91,8 @@ struct cnxk_sso_evdev {\n \tuint32_t min_dequeue_timeout_ns;\n \tuint32_t max_dequeue_timeout_ns;\n \tint32_t max_num_events;\n-\tuint64_t *fc_mem;\n \tuint64_t xaq_lmt;\n-\tuint64_t nb_xaq_cfg;\n \trte_iova_t fc_iova;\n-\tstruct rte_mempool *xaq_pool;\n \tuint64_t rx_offloads;\n \tuint64_t tx_offloads;\n \tuint64_t adptr_xae_cnt;\n", "prefixes": [ "2/2" ] }