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GET /api/patches/97790/?format=api
{ "id": 97790, "url": "http://patchwork.dpdk.org/api/patches/97790/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/cc2543c44e71ed56c0a98c62acc8ac12a8b8b954.1630584303.git.sthotton@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<cc2543c44e71ed56c0a98c62acc8ac12a8b8b954.1630584303.git.sthotton@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/cc2543c44e71ed56c0a98c62acc8ac12a8b8b954.1630584303.git.sthotton@marvell.com", "date": "2021-09-02T12:17:22", "name": "[v2,6/8] event/cnxk: add cn9k crypto adapter fast path ops", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bd8fd5ddc4400e0a3a4ff9398a944f417521cfe4", "submitter": { "id": 2049, "url": "http://patchwork.dpdk.org/api/people/2049/?format=api", "name": "Shijith Thotton", "email": "sthotton@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/cc2543c44e71ed56c0a98c62acc8ac12a8b8b954.1630584303.git.sthotton@marvell.com/mbox/", "series": [ { "id": 18627, "url": "http://patchwork.dpdk.org/api/series/18627/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18627", "date": "2021-09-02T12:17:16", "name": "Crypto adapter support for Marvell CNXK driver", "version": 2, "mbox": "http://patchwork.dpdk.org/series/18627/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/97790/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/97790/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C50F0A0C47;\n\tThu, 2 Sep 2021 14:21:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D08D040142;\n\tThu, 2 Sep 2021 14:21:54 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 7526D410D8\n for <dev@dpdk.org>; Thu, 2 Sep 2021 14:21:52 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1825LIYk028455\n for <dev@dpdk.org>; Thu, 2 Sep 2021 05:21:51 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 3atrd2he72-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 02 Sep 2021 05:21:51 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 2 Sep 2021 05:21:50 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 2 Sep 2021 05:21:49 -0700", "from localhost.localdomain (unknown [10.28.34.29])\n by maili.marvell.com (Postfix) with ESMTP id 6FBCB3F705E;\n Thu, 2 Sep 2021 05:21:47 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=1YX+bNi3QsDyoJusbFa+ASuVCz8KF4BtFL8jilQXmlk=;\n b=FEZxiutuZ7tDBHY99+8M2LGDjpYcWupWcJJElRReHJbEyKcDJG6J6yVwiw3d9CQ3p2vH\n Ie/feexDsiaP7awLRdbrkW6AC26IWDgKFzOVpFFDepknNUQ2eRXi7BmnWfFL2cnEDqjO\n fSLeuaoQXV3KOaayNL04Myue9NzyIUsZarGykrhhsXultpcgPqFdmskXNJ9g7dcrXKXa\n ul7BPkQ3T46BlbxxtvpagUBLHislmCtpbD4IKSmkpwfe/kZf47TiXJ7l7A1LvXe0EPkd\n Z7Iwg+7Dali0A/QD//XrNnYZgxQbXZJTEmMOClraI8SeiTbx2QzyNLmDHsrCLf78a0dq qA==", "From": "Shijith Thotton <sthotton@marvell.com>", "To": "<dev@dpdk.org>", "CC": "Shijith Thotton <sthotton@marvell.com>, <jerinj@marvell.com>,\n <ndabilpuram@marvell.com>, <anoobj@marvell.com>,\n <pbhagavatula@marvell.com>, <gakhil@marvell.com>", "Date": "Thu, 2 Sep 2021 17:47:22 +0530", "Message-ID": "\n <cc2543c44e71ed56c0a98c62acc8ac12a8b8b954.1630584303.git.sthotton@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1630584303.git.sthotton@marvell.com>", "References": "<cover.1630315730.git.sthotton@marvell.com>\n <cover.1630584303.git.sthotton@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "gKJXBM6mPNiDGve2YHFPDtNHjIJeVS1f", "X-Proofpoint-ORIG-GUID": "gKJXBM6mPNiDGve2YHFPDtNHjIJeVS1f", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-02_04,2021-09-02_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH v2 6/8] event/cnxk: add cn9k crypto adapter fast\n path ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Set crypto adapter enqueue and dequeue operations for CN9K.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/event/cnxk/cn9k_eventdev.c | 94 +++++++++++++++++++-\n drivers/event/cnxk/cn9k_worker.c | 22 +++++\n drivers/event/cnxk/cn9k_worker.h | 41 ++++++++-\n drivers/event/cnxk/cn9k_worker_deq_ca.c | 65 ++++++++++++++\n drivers/event/cnxk/cn9k_worker_dual_deq_ca.c | 75 ++++++++++++++++\n drivers/event/cnxk/meson.build | 2 +\n 6 files changed, 292 insertions(+), 7 deletions(-)\n create mode 100644 drivers/event/cnxk/cn9k_worker_deq_ca.c\n create mode 100644 drivers/event/cnxk/cn9k_worker_dual_deq_ca.c", "diff": "diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex cab00ed3ca..34247e6c74 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -363,6 +363,20 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n #undef R\n \t};\n \n+\tconst event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t sso_hws_deq_ca_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_burst_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n \tconst event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {\n #define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n \t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,\n@@ -390,7 +404,22 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name,\n \t\t\tNIX_RX_FASTPATH_MODES\n #undef R\n-\t\t};\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_deq_ca_seg_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_burst_##name,\n+\t\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n \n \t/* Dual WS modes */\n \tconst event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2] = {\n@@ -420,7 +449,22 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name,\n \t\t\tNIX_RX_FASTPATH_MODES\n #undef R\n-\t\t};\n+\t};\n+\n+\tconst event_dequeue_t sso_hws_dual_deq_ca[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_dual_deq_ca_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_burst_##name,\n+\t\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n \n \tconst event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2] = {\n #define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n@@ -452,6 +496,21 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n #undef R\n \t\t};\n \n+\tconst event_dequeue_t sso_hws_dual_deq_ca_seg[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_##name,\n+\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tconst event_dequeue_burst_t\n+\t\tsso_hws_dual_deq_ca_seg_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\t[f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_burst_##name,\n+\t\t\tNIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n \t/* Tx modes */\n \tconst event_tx_adapter_enqueue\n \t\tsso_hws_tx_adptr_enq[2][2][2][2][2][2] = {\n@@ -499,6 +558,12 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,\n \t\t\t\t\t sso_hws_deq_tmo_seg_burst);\n \t\t}\n+\t\tif (dev->is_ca_internal_port) {\n+\t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,\n+\t\t\t\t\t sso_hws_deq_ca_seg);\n+\t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,\n+\t\t\t\t\t sso_hws_deq_ca_seg_burst);\n+\t\t}\n \t} else {\n \t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);\n \t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,\n@@ -509,7 +574,14 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,\n \t\t\t\t\t sso_hws_deq_tmo_burst);\n \t\t}\n+\t\tif (dev->is_ca_internal_port) {\n+\t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,\n+\t\t\t\t\t sso_hws_deq_ca);\n+\t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,\n+\t\t\t\t\t sso_hws_deq_ca_burst);\n+\t\t}\n \t}\n+\tevent_dev->ca_enqueue = cn9k_sso_hws_ca_enq;\n \n \tif (dev->tx_offloads & NIX_TX_MULTI_SEG_F)\n \t\tCN9K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,\n@@ -524,6 +596,7 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\tevent_dev->enqueue_new_burst = cn9k_sso_hws_dual_enq_new_burst;\n \t\tevent_dev->enqueue_forward_burst =\n \t\t\tcn9k_sso_hws_dual_enq_fwd_burst;\n+\t\tevent_dev->ca_enqueue = cn9k_sso_hws_dual_ca_enq;\n \n \t\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n \t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,\n@@ -537,6 +610,13 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\t\t\t\tdev, event_dev->dequeue_burst,\n \t\t\t\t\tsso_hws_dual_deq_tmo_seg_burst);\n \t\t\t}\n+\t\t\tif (dev->is_ca_internal_port) {\n+\t\t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,\n+\t\t\t\t\t\t sso_hws_dual_deq_ca_seg);\n+\t\t\t\tCN9K_SET_EVDEV_DEQ_OP(\n+\t\t\t\t\tdev, event_dev->dequeue_burst,\n+\t\t\t\t\tsso_hws_dual_deq_ca_seg_burst);\n+\t\t\t}\n \t\t} else {\n \t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,\n \t\t\t\t\t sso_hws_dual_deq);\n@@ -549,6 +629,13 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\t\t\t\tdev, event_dev->dequeue_burst,\n \t\t\t\t\tsso_hws_dual_deq_tmo_burst);\n \t\t\t}\n+\t\t\tif (dev->is_ca_internal_port) {\n+\t\t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,\n+\t\t\t\t\t\t sso_hws_dual_deq_ca);\n+\t\t\t\tCN9K_SET_EVDEV_DEQ_OP(\n+\t\t\t\t\tdev, event_dev->dequeue_burst,\n+\t\t\t\t\tsso_hws_dual_deq_ca_burst);\n+\t\t\t}\n \t\t}\n \n \t\tif (dev->tx_offloads & NIX_TX_MULTI_SEG_F)\n@@ -935,7 +1022,8 @@ cn9k_crypto_adapter_caps_get(const struct rte_eventdev *event_dev,\n \tCNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, \"event_cn9k\");\n \tCNXK_VALID_DEV_OR_ERR_RET(cdev->device, \"crypto_cn9k\");\n \n-\t*caps = 0;\n+\t*caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD |\n+\t\tRTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA;\n \n \treturn 0;\n }\ndiff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c\nindex 538bc4b0b3..32f7cc0343 100644\n--- a/drivers/event/cnxk/cn9k_worker.c\n+++ b/drivers/event/cnxk/cn9k_worker.c\n@@ -5,6 +5,7 @@\n #include \"roc_api.h\"\n \n #include \"cn9k_worker.h\"\n+#include \"cn9k_cryptodev_ops.h\"\n \n uint16_t __rte_hot\n cn9k_sso_hws_enq(void *port, const struct rte_event *ev)\n@@ -117,3 +118,24 @@ cn9k_sso_hws_dual_enq_fwd_burst(void *port, const struct rte_event ev[],\n \n \treturn 1;\n }\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n+{\n+\tstruct cn9k_sso_hws *ws = port;\n+\n+\tRTE_SET_USED(nb_events);\n+\n+\treturn cn9k_cpt_crypto_adapter_enqueue(ws->tag_op, ev->event_ptr);\n+}\n+\n+uint16_t __rte_hot\n+cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n+{\n+\tstruct cn9k_sso_hws_dual *dws = port;\n+\n+\tRTE_SET_USED(nb_events);\n+\n+\treturn cn9k_cpt_crypto_adapter_enqueue(dws->ws_state[!dws->vws].tag_op,\n+\t\t\t\t\t ev->event_ptr);\n+}\ndiff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h\nindex 9b2a0bf882..3e8f214904 100644\n--- a/drivers/event/cnxk/cn9k_worker.h\n+++ b/drivers/event/cnxk/cn9k_worker.h\n@@ -8,6 +8,7 @@\n #include \"cnxk_ethdev.h\"\n #include \"cnxk_eventdev.h\"\n #include \"cnxk_worker.h\"\n+#include \"cn9k_cryptodev_ops.h\"\n \n #include \"cn9k_ethdev.h\"\n #include \"cn9k_rx.h\"\n@@ -187,8 +188,12 @@ cn9k_sso_hws_dual_get_work(struct cn9k_sso_hws_state *ws,\n \t\t (gw.u64[0] & 0xffffffff);\n \n \tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n-\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n-\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\tif ((flags & CPT_RX_WQE_F) &&\n+\t\t (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_CRYPTODEV)) {\n+\t\t\tgw.u64[1] = cn9k_cpt_crypto_adapter_dequeue(gw.u64[1]);\n+\t\t} else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t\t RTE_EVENT_TYPE_ETHDEV) {\n \t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n \n \t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n@@ -260,8 +265,12 @@ cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev,\n \t\t (gw.u64[0] & 0xffffffff);\n \n \tif (CNXK_TT_FROM_EVENT(gw.u64[0]) != SSO_TT_EMPTY) {\n-\t\tif (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n-\t\t RTE_EVENT_TYPE_ETHDEV) {\n+\t\tif ((flags & CPT_RX_WQE_F) &&\n+\t\t (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t RTE_EVENT_TYPE_CRYPTODEV)) {\n+\t\t\tgw.u64[1] = cn9k_cpt_crypto_adapter_dequeue(gw.u64[1]);\n+\t\t} else if (CNXK_EVENT_TYPE_FROM_TAG(gw.u64[0]) ==\n+\t\t\t RTE_EVENT_TYPE_ETHDEV) {\n \t\t\tuint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]);\n \n \t\t\tgw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]);\n@@ -366,6 +375,10 @@ uint16_t __rte_hot cn9k_sso_hws_dual_enq_new_burst(void *port,\n uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port,\n \t\t\t\t\t\t const struct rte_event ev[],\n \t\t\t\t\t\t uint16_t nb_events);\n+uint16_t __rte_hot cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[],\n+\t\t\t\t uint16_t nb_events);\n+uint16_t __rte_hot cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[],\n+\t\t\t\t\t uint16_t nb_events);\n \n #define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n \tuint16_t __rte_hot cn9k_sso_hws_deq_##name( \\\n@@ -378,6 +391,11 @@ uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port,\n \tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_burst_##name( \\\n \t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n \t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_ca_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_ca_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n \tuint16_t __rte_hot cn9k_sso_hws_deq_seg_##name( \\\n \t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n \tuint16_t __rte_hot cn9k_sso_hws_deq_seg_burst_##name( \\\n@@ -386,6 +404,11 @@ uint16_t __rte_hot cn9k_sso_hws_dual_enq_fwd_burst(void *port,\n \tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_##name( \\\n \t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n \tuint16_t __rte_hot cn9k_sso_hws_deq_tmo_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_burst_##name( \\\n \t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n \t\tuint64_t timeout_ticks);\n \n@@ -403,6 +426,11 @@ NIX_RX_FASTPATH_MODES\n \tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_burst_##name( \\\n \t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n \t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n \tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_##name( \\\n \t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n \tuint16_t __rte_hot cn9k_sso_hws_dual_deq_seg_burst_##name( \\\n@@ -411,6 +439,11 @@ NIX_RX_FASTPATH_MODES\n \tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_##name( \\\n \t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n \tuint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks); \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_burst_##name( \\\n \t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n \t\tuint64_t timeout_ticks);\n \ndiff --git a/drivers/event/cnxk/cn9k_worker_deq_ca.c b/drivers/event/cnxk/cn9k_worker_deq_ca.c\nnew file mode 100644\nindex 0000000000..dbdbba17db\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker_deq_ca.c\n@@ -0,0 +1,65 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_ca_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_get_work(ws, ev, flags | CPT_RX_WQE_F, \\\n+\t\t\t\t\t ws->lookup_mem); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_ca_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_deq_ca_##name(port, ev, timeout_ticks); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws *ws = port; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tif (ws->swtag_req) { \\\n+\t\t\tws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait(ws->tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_get_work( \\\n+\t\t\tws, ev, flags | NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F, \\\n+\t\t\tws->lookup_mem); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_deq_ca_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_deq_ca_seg_##name(port, ev, \\\n+\t\t\t\t\t\t timeout_ticks); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/cn9k_worker_dual_deq_ca.c b/drivers/event/cnxk/cn9k_worker_dual_deq_ca.c\nnew file mode 100644\nindex 0000000000..dc9191fe80\n--- /dev/null\n+++ b/drivers/event/cnxk/cn9k_worker_dual_deq_ca.c\n@@ -0,0 +1,75 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cn9k_worker.h\"\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_worker.h\"\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags) \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t gw; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tgw = cn9k_sso_hws_dual_get_work(&dws->ws_state[dws->vws], \\\n+\t\t\t\t\t\t&dws->ws_state[!dws->vws], ev, \\\n+\t\t\t\t\t\tflags | CPT_RX_WQE_F, \\\n+\t\t\t\t\t\tdws->lookup_mem, dws->tstamp); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\treturn gw; \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_dual_deq_ca_##name(port, ev, \\\n+\t\t\t\t\t\t timeout_ticks); \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_##name( \\\n+\t\tvoid *port, struct rte_event *ev, uint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tstruct cn9k_sso_hws_dual *dws = port; \\\n+\t\tuint16_t gw; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tRTE_SET_USED(timeout_ticks); \\\n+\t\tif (dws->swtag_req) { \\\n+\t\t\tdws->swtag_req = 0; \\\n+\t\t\tcnxk_sso_hws_swtag_wait( \\\n+\t\t\t\tdws->ws_state[!dws->vws].tag_op); \\\n+\t\t\treturn 1; \\\n+\t\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\tgw = cn9k_sso_hws_dual_get_work( \\\n+\t\t\t&dws->ws_state[dws->vws], &dws->ws_state[!dws->vws], \\\n+\t\t\tev, flags | NIX_RX_MULTI_SEG_F | CPT_RX_WQE_F, \\\n+\t\t\tdws->lookup_mem, dws->tstamp); \\\n+\t\tdws->vws = !dws->vws; \\\n+\t\treturn gw; \\\n+\t} \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_seg_burst_##name( \\\n+\t\tvoid *port, struct rte_event ev[], uint16_t nb_events, \\\n+\t\tuint64_t timeout_ticks) \\\n+\t{ \\\n+\t\tRTE_SET_USED(nb_events); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t\treturn cn9k_sso_hws_dual_deq_ca_seg_##name(port, ev, \\\n+\t\t\t\t\t\t\t timeout_ticks); \\\n+\t}\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nindex 1155e18ba7..ffbc0ce0f4 100644\n--- a/drivers/event/cnxk/meson.build\n+++ b/drivers/event/cnxk/meson.build\n@@ -13,9 +13,11 @@ sources = files(\n 'cn9k_worker.c',\n 'cn9k_worker_deq.c',\n 'cn9k_worker_deq_burst.c',\n+ 'cn9k_worker_deq_ca.c',\n 'cn9k_worker_deq_tmo.c',\n 'cn9k_worker_dual_deq.c',\n 'cn9k_worker_dual_deq_burst.c',\n+ 'cn9k_worker_dual_deq_ca.c',\n 'cn9k_worker_dual_deq_tmo.c',\n 'cn9k_worker_tx_enq.c',\n 'cn9k_worker_tx_enq_seg.c',\n", "prefixes": [ "v2", "6/8" ] }