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GET /api/patches/98046/?format=api
{ "id": 98046, "url": "http://patchwork.dpdk.org/api/patches/98046/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210906075450.1452123-9-skori@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210906075450.1452123-9-skori@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210906075450.1452123-9-skori@marvell.com", "date": "2021-09-06T07:54:32", "name": "[09/27] common/cnxk: support RoC API to setup precolor table", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "56c57c4a0c065c712b670d2057cb4f3494ee6b87", "submitter": { "id": 1318, "url": "http://patchwork.dpdk.org/api/people/1318/?format=api", "name": "Sunil Kumar Kori", "email": "skori@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210906075450.1452123-9-skori@marvell.com/mbox/", "series": [ { "id": 18696, "url": "http://patchwork.dpdk.org/api/series/18696/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18696", "date": "2021-09-06T07:54:24", "name": "[01/27] common/cnxk: update policer MBOX APIs and HW definitions", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18696/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/98046/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/98046/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 49BA6A0C4D;\n\tMon, 6 Sep 2021 09:55:48 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 540AF410F1;\n\tMon, 6 Sep 2021 09:55:22 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id C5DC441144\n for <dev@dpdk.org>; Mon, 6 Sep 2021 09:55:20 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id\n 185MxZEJ021315;\n Mon, 6 Sep 2021 00:55:18 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 3aw2sp1sm6-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 06 Sep 2021 00:55:18 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 6 Sep 2021 00:55:16 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 6 Sep 2021 00:55:16 -0700", "from localhost.localdomain (unknown [10.28.34.25])\n by maili.marvell.com (Postfix) with ESMTP id DF36F3F70A0;\n Mon, 6 Sep 2021 00:55:14 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=unzlZV6jnkol84eJkznHKhS/OZnZr7c+/XRS7jnBB6g=;\n b=Ekn4MY3l8itGRdnuZ2JaS3pWVWwV/wBgZIWywL3bkMK4ClLE0KiYgbeQGiW6dRilkIX2\n VJB9KC8scSciHg0i19PXaWXXbkvg2/oGMX1oDIcgjUoiSpJMXNEEQ9vhLSXs7qvW1RBi\n 9BubQKIM3d7uOQ32UmUxxE7coD9mQWasulVUCyNBk+6xmMWjNlskJtdmrD9ObHHpG2uG\n TJkrSlaH+kne20jdMoPiCxD+B8ut4Wtqqq16oHvpRcr3o82HeTKYVpnEB2gO10W4r2zL\n qZcWAFGWpWp4qF2FiDva+ZqnSt4BIomHj3LkKmMfHtoQ29FU9W4nP4/IakuHRnVIbILS cQ==", "From": "<skori@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>", "Date": "Mon, 6 Sep 2021 13:24:32 +0530", "Message-ID": "<20210906075450.1452123-9-skori@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210906075450.1452123-1-skori@marvell.com>", "References": "<20210906075450.1452123-1-skori@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "5pKi4wHe0ZEOZh_AOaKQyEmWD3KjAJTW", "X-Proofpoint-ORIG-GUID": "5pKi4wHe0ZEOZh_AOaKQyEmWD3KjAJTW", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-06_02,2021-09-03_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 09/27] common/cnxk: support RoC API to setup\n precolor table", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nFor initial coloring of input packet, CN10K platform maintains\nprecolor table for VLAN, DSCP and Generic. Implement RoC\ninterface to setup pre color table.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 20 ++++\n drivers/common/cnxk/roc_nix_bpf.c | 188 ++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 1 +\n 3 files changed, 209 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 19c376e9c4..36f6a35c50 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -87,6 +87,15 @@ enum roc_nix_bpf_level_flag {\n \tROC_NIX_BPF_LEVEL_F_TOP = BIT(2),\n };\n \n+enum roc_nix_bpf_pc_mode {\n+\tROC_NIX_BPF_PC_MODE_VLAN_INNER,\n+\tROC_NIX_BPF_PC_MODE_VLAN_OUTER,\n+\tROC_NIX_BPF_PC_MODE_DSCP_INNER,\n+\tROC_NIX_BPF_PC_MODE_DSCP_OUTER,\n+\tROC_NIX_BPF_PC_MODE_GEN_INNER,\n+\tROC_NIX_BPF_PC_MODE_GEN_OUTER\n+};\n+\n enum roc_nix_bpf_color {\n \tROC_NIX_BPF_COLOR_GREEN,\n \tROC_NIX_BPF_COLOR_YELLOW,\n@@ -149,6 +158,13 @@ struct roc_nix_bpf_objs {\n \tuint16_t ids[ROC_NIX_BPF_PER_PFFUNC];\n };\n \n+struct roc_nix_bpf_precolor {\n+#define ROC_NIX_BPF_PRE_COLOR_MAX 64\n+\tuint8_t count;\n+\tenum roc_nix_bpf_pc_mode mode;\n+\tenum roc_nix_bpf_color color[ROC_NIX_BPF_PRE_COLOR_MAX];\n+};\n+\n struct roc_nix_vlan_config {\n \tuint32_t type;\n \tunion {\n@@ -610,6 +626,10 @@ int __roc_api roc_nix_bpf_ena_dis(struct roc_nix *roc_nix, uint16_t id,\n int __roc_api roc_nix_bpf_dump(struct roc_nix *roc_nix, uint16_t id,\n \t\t\t enum roc_nix_bpf_level_flag lvl_flag);\n \n+int __roc_api roc_nix_bpf_pre_color_tbl_setup(\n+\tstruct roc_nix *roc_nix, uint16_t id,\n+\tenum roc_nix_bpf_level_flag lvl_flag, struct roc_nix_bpf_precolor *tbl);\n+\n uint8_t __roc_api\n roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag lvl_flag);\n \ndiff --git a/drivers/common/cnxk/roc_nix_bpf.c b/drivers/common/cnxk/roc_nix_bpf.c\nindex 2b2be20491..aae6f0ec77 100644\n--- a/drivers/common/cnxk/roc_nix_bpf.c\n+++ b/drivers/common/cnxk/roc_nix_bpf.c\n@@ -9,6 +9,10 @@\n #define NIX_MAX_BPF_COUNT_MID_LAYER 8\n #define NIX_MAX_BPF_COUNT_TOP_LAYER 1\n \n+#define NIX_BPF_PRECOLOR_GEN_TABLE_SIZE\t 16\n+#define NIX_BPF_PRECOLOR_VLAN_TABLE_SIZE 16\n+#define NIX_BPF_PRECOLOR_DSCP_TABLE_SIZE 64\n+\n #define NIX_BPF_LEVEL_F_MASK \\\n \t(ROC_NIX_BPF_LEVEL_F_LEAF | ROC_NIX_BPF_LEVEL_F_MID | \\\n \t ROC_NIX_BPF_LEVEL_F_TOP)\n@@ -177,6 +181,103 @@ nix_lf_bpf_dump(__io struct nix_band_prof_s *bpf)\n \t\t (uint64_t)bpf->red_octs_drop);\n }\n \n+static inline void\n+nix_precolor_conv_table_write(struct roc_nix *roc_nix, uint64_t val,\n+\t\t\t uint32_t off)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tint64_t *addr;\n+\n+\taddr = PLT_PTR_ADD(nix->base, off);\n+\tplt_write64(val, addr);\n+}\n+\n+static uint8_t\n+nix_precolor_vlan_table_update(struct roc_nix *roc_nix,\n+\t\t\t struct roc_nix_bpf_precolor *tbl)\n+{\n+\tuint64_t val = 0, i;\n+\tuint8_t tn_ena;\n+\tuint32_t off;\n+\n+\tfor (i = 0; i < tbl->count; i++)\n+\t\tval |= (((uint64_t)tbl->color[i]) << (2 * i));\n+\n+\tif (tbl->mode == ROC_NIX_BPF_PC_MODE_VLAN_INNER) {\n+\t\toff = NIX_LF_RX_VLAN1_COLOR_CONV;\n+\t\ttn_ena = true;\n+\t} else {\n+\t\toff = NIX_LF_RX_VLAN0_COLOR_CONV;\n+\t\ttn_ena = false;\n+\t}\n+\n+\tnix_precolor_conv_table_write(roc_nix, val, off);\n+\treturn tn_ena;\n+}\n+\n+static uint8_t\n+nix_precolor_inner_dscp_table_update(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_bpf_precolor *tbl)\n+{\n+\tuint64_t val_lo = 0, val_hi = 0, i, j;\n+\n+\tfor (i = 0, j = 0; i < (tbl->count / 2); i++, j++)\n+\t\tval_lo |= (((uint64_t)tbl->color[i]) << (2 * j));\n+\n+\tfor (j = 0; i < tbl->count; i++, j++)\n+\t\tval_hi |= (((uint64_t)tbl->color[i]) << (2 * j));\n+\n+\tnix_precolor_conv_table_write(roc_nix, val_lo,\n+\t\t\t\t NIX_LF_RX_IIP_COLOR_CONV_LO);\n+\tnix_precolor_conv_table_write(roc_nix, val_hi,\n+\t\t\t\t NIX_LF_RX_IIP_COLOR_CONV_HI);\n+\n+\treturn true;\n+}\n+\n+static uint8_t\n+nix_precolor_outer_dscp_table_update(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_bpf_precolor *tbl)\n+{\n+\tuint64_t val_lo = 0, val_hi = 0, i, j;\n+\n+\tfor (i = 0, j = 0; i < (tbl->count / 2); i++, j++)\n+\t\tval_lo |= (((uint64_t)tbl->color[i]) << (2 * j));\n+\n+\tfor (j = 0; i < tbl->count; i++, j++)\n+\t\tval_hi |= (((uint64_t)tbl->color[i]) << (2 * j));\n+\n+\tnix_precolor_conv_table_write(roc_nix, val_lo,\n+\t\t\t\t NIX_LF_RX_OIP_COLOR_CONV_LO);\n+\tnix_precolor_conv_table_write(roc_nix, val_hi,\n+\t\t\t\t NIX_LF_RX_OIP_COLOR_CONV_HI);\n+\n+\treturn false;\n+}\n+\n+static uint8_t\n+nix_precolor_gen_table_update(struct roc_nix *roc_nix,\n+\t\t\t struct roc_nix_bpf_precolor *tbl)\n+{\n+\tuint64_t val = 0, i;\n+\tuint8_t tn_ena;\n+\tuint32_t off;\n+\n+\tfor (i = 0; i < tbl->count; i++)\n+\t\tval |= (((uint64_t)tbl->color[i]) << (2 * i));\n+\n+\tif (tbl->mode == ROC_NIX_BPF_PC_MODE_GEN_INNER) {\n+\t\toff = NIX_LF_RX_GEN_COLOR_CONVX(1);\n+\t\ttn_ena = true;\n+\t} else {\n+\t\toff = NIX_LF_RX_GEN_COLOR_CONVX(0);\n+\t\ttn_ena = false;\n+\t}\n+\n+\tnix_precolor_conv_table_write(roc_nix, val, off);\n+\treturn tn_ena;\n+}\n+\n uint8_t\n roc_nix_bpf_level_to_idx(enum roc_nix_bpf_level_flag level_f)\n {\n@@ -555,3 +656,90 @@ roc_nix_bpf_dump(struct roc_nix *roc_nix, uint16_t id,\n \n \treturn rc;\n }\n+\n+int\n+roc_nix_bpf_pre_color_tbl_setup(struct roc_nix *roc_nix, uint16_t id,\n+\t\t\t\tenum roc_nix_bpf_level_flag lvl_flag,\n+\t\t\t\tstruct roc_nix_bpf_precolor *tbl)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix_cn10k_aq_enq_req *aq;\n+\tuint8_t pc_mode, tn_ena;\n+\tuint8_t level_idx;\n+\tint rc;\n+\n+\tif (!tbl || !tbl->count)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tif (roc_model_is_cn9k())\n+\t\treturn NIX_ERR_HW_NOTSUP;\n+\n+\tlevel_idx = roc_nix_bpf_level_to_idx(lvl_flag);\n+\tif (level_idx == ROC_NIX_BPF_LEVEL_IDX_INVALID)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tswitch (tbl->mode) {\n+\tcase ROC_NIX_BPF_PC_MODE_VLAN_INNER:\n+\tcase ROC_NIX_BPF_PC_MODE_VLAN_OUTER:\n+\t\tif (tbl->count != NIX_BPF_PRECOLOR_VLAN_TABLE_SIZE) {\n+\t\t\tplt_err(\"Table size must be %d\",\n+\t\t\t\tNIX_BPF_PRECOLOR_VLAN_TABLE_SIZE);\n+\t\t\trc = NIX_ERR_PARAM;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\ttn_ena = nix_precolor_vlan_table_update(roc_nix, tbl);\n+\t\tpc_mode = NIX_RX_BAND_PROF_PC_MODE_VLAN;\n+\t\tbreak;\n+\tcase ROC_NIX_BPF_PC_MODE_DSCP_INNER:\n+\t\tif (tbl->count != NIX_BPF_PRECOLOR_DSCP_TABLE_SIZE) {\n+\t\t\tplt_err(\"Table size must be %d\",\n+\t\t\t\tNIX_BPF_PRECOLOR_DSCP_TABLE_SIZE);\n+\t\t\trc = NIX_ERR_PARAM;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\ttn_ena = nix_precolor_inner_dscp_table_update(roc_nix, tbl);\n+\t\tpc_mode = NIX_RX_BAND_PROF_PC_MODE_DSCP;\n+\t\tbreak;\n+\tcase ROC_NIX_BPF_PC_MODE_DSCP_OUTER:\n+\t\tif (tbl->count != NIX_BPF_PRECOLOR_DSCP_TABLE_SIZE) {\n+\t\t\tplt_err(\"Table size must be %d\",\n+\t\t\t\tNIX_BPF_PRECOLOR_DSCP_TABLE_SIZE);\n+\t\t\trc = NIX_ERR_PARAM;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\ttn_ena = nix_precolor_outer_dscp_table_update(roc_nix, tbl);\n+\t\tpc_mode = NIX_RX_BAND_PROF_PC_MODE_DSCP;\n+\t\tbreak;\n+\tcase ROC_NIX_BPF_PC_MODE_GEN_INNER:\n+\tcase ROC_NIX_BPF_PC_MODE_GEN_OUTER:\n+\t\tif (tbl->count != NIX_BPF_PRECOLOR_GEN_TABLE_SIZE) {\n+\t\t\tplt_err(\"Table size must be %d\",\n+\t\t\t\tNIX_BPF_PRECOLOR_GEN_TABLE_SIZE);\n+\t\t\trc = NIX_ERR_PARAM;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\ttn_ena = nix_precolor_gen_table_update(roc_nix, tbl);\n+\t\tpc_mode = NIX_RX_BAND_PROF_PC_MODE_GEN;\n+\t\tbreak;\n+\tdefault:\n+\t\trc = NIX_ERR_PARAM;\n+\t\tgoto exit;\n+\t}\n+\n+\t/* Update corresponding bandwidth profile too */\n+\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\tif (aq == NULL)\n+\t\treturn -ENOSPC;\n+\taq->qidx = (sw_to_hw_lvl_map[level_idx] << 14) | id;\n+\taq->ctype = NIX_AQ_CTYPE_BAND_PROF;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\taq->prof.pc_mode = pc_mode;\n+\taq->prof.tnl_ena = tn_ena;\n+\taq->prof_mask.pc_mode = ~(aq->prof_mask.pc_mode);\n+\taq->prof_mask.tnl_ena = ~(aq->prof_mask.tnl_ena);\n+\n+\treturn mbox_process(mbox);\n+\n+exit:\n+\treturn rc;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex a201f6a755..984c239766 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -82,6 +82,7 @@ INTERNAL {\n \troc_nix_bpf_free;\n \troc_nix_bpf_free_all;\n \troc_nix_bpf_level_to_idx;\n+\troc_nix_bpf_pre_color_tbl_setup;\n \troc_nix_cq_dump;\n \troc_nix_cq_fini;\n \troc_nix_cq_init;\n", "prefixes": [ "09/27" ] }