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GET /api/patches/99693/?format=api
{ "id": 99693, "url": "http://patchwork.dpdk.org/api/patches/99693/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210926111904.237736-11-xuemingl@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210926111904.237736-11-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210926111904.237736-11-xuemingl@nvidia.com", "date": "2021-09-26T11:19:03", "name": "[10/11] net/mlx5: remove Rx queue data list from device", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "61401462fa0d3bec9b2a483cc83962cb505f1bee", "submitter": { "id": 1904, "url": "http://patchwork.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210926111904.237736-11-xuemingl@nvidia.com/mbox/", "series": [ { "id": 19166, "url": "http://patchwork.dpdk.org/api/series/19166/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=19166", "date": "2021-09-26T11:18:53", "name": "net/mlx5: support shared Rx queue", "version": 1, "mbox": "http://patchwork.dpdk.org/series/19166/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/99693/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/99693/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 034A2A0547;\n\tSun, 26 Sep 2021 13:20:38 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C7328410DA;\n\tSun, 26 Sep 2021 13:20:37 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2070.outbound.protection.outlook.com [40.107.236.70])\n by mails.dpdk.org (Postfix) with ESMTP id 1F2D340E78\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Xueming Li <xuemingl@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<xuemingl@nvidia.com>, Lior Margalit <lmargalit@nvidia.com>, Matan Azrad\n <matan@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Sun, 26 Sep 2021 19:19:03 +0800", "Message-ID": "<20210926111904.237736-11-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20210926111904.237736-1-xuemingl@nvidia.com>", "References": "<20210926111904.237736-1-xuemingl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n DRHQMAIL107.nvidia.com (10.27.9.16)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "2b2357e8-691f-4367-3959-08d980dfa92f", "X-MS-TrafficTypeDiagnostic": "CH2PR12MB4264:", "X-Microsoft-Antispam-PRVS": "\n <CH2PR12MB42642782984B45C19677FDCBA1A69@CH2PR12MB4264.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7219;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n UzIUVsBCPJ/xVhRHIFVR3c77u9wW9yFce2taksAmaIlxP6yPr9GRiqCL787VGrvRT8bj5cLiQr/kl+HwKMkJ3pkwy+Gw4mgFklPRpVB6rwzNDzmxZ7lSusErPCR6DDQlNvne+8BdTtOc4GdzCG60UbJyYJGHqlCg+OKCg8GslspZ+Md92wcMa4vmGXN4Ar0p0rfo5zyuWtwLS6YaCPyGV2VajiZa4Sw8TD+t64qdYRHYTEulAQAO+Wgr6SDRVWlkNPcSCLiyRHRXtvPtZ1Isx1wt3LcS9gBgxtCiovF8HVNCs4ZxBaaU0eHdtHRJeb5brTHn6HO7OOTjlNre7xmbdxV9avTJwNe6YL+Q7fNG4RhAjPC45q+rJ2uOl6Va648s5s3QSD3sl3Nbkuz/0ZR0JQl/3h0QvhSaK4EqUzjoh8L2Fy5IWzbBlYk2Ncoxu73CrpsPe5Y+K5e7alwwsR0DaeU/HdFXVl4w6S810sr8Vz+RSnU3KP8Gns73zkFphAT9C13RfIRiYG72IMOMqnJDQUJpn7yt7mtvoJpurHqXv0p2RpNzNIRkz+8i6DsrTYz2GwqVAUnKL9HgE3rQrnXu9QwcxDZAqXIbyBIR8SW+4clWK1W7dHFFMNLKIaqessGhIfCECvo23IGBXCXeVYpHb+pfny6Lc8yG4j1ji1GgI5J2eqsPO2xFqMJR0nKuBC9JRjPOCVqzx8Nw+nO4Af2QcDNLmUlqvixrDw7q+im8BbeOcylebp1T/Y+5K5PrmNZ+", "X-Forefront-Antispam-Report": "CIP:216.228.112.35; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid04.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(26005)(36906005)(82310400003)(4326008)(107886003)(6666004)(316002)(1076003)(2906002)(86362001)(54906003)(426003)(6286002)(30864003)(6916009)(47076005)(8936002)(336012)(70206006)(2616005)(70586007)(8676002)(36860700001)(7696005)(83380400001)(16526019)(356005)(55016002)(36756003)(186003)(508600001)(7636003)(5660300002)(21314003)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 Sep 2021 11:20:35.1683 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2b2357e8-691f-4367-3959-08d980dfa92f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT048.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB4264", "Subject": "[dpdk-dev] [PATCH 10/11] net/mlx5: remove Rx queue data list from\n device", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Rx queue data list(priv->rxqs) can be replaced by Rx queue\nlist(priv->rxq_privs), removes it and replace with universal wrapper\nAPI.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_verbs.c | 7 ++---\n drivers/net/mlx5/mlx5.c | 10 +------\n drivers/net/mlx5/mlx5.h | 1 -\n drivers/net/mlx5/mlx5_devx.c | 13 +++++----\n drivers/net/mlx5/mlx5_ethdev.c | 6 +---\n drivers/net/mlx5/mlx5_flow.c | 45 +++++++++++++++--------------\n drivers/net/mlx5/mlx5_rss.c | 6 ++--\n drivers/net/mlx5/mlx5_rx.c | 16 ++++------\n drivers/net/mlx5/mlx5_rx.h | 9 +++---\n drivers/net/mlx5/mlx5_rxq.c | 23 ++++++---------\n drivers/net/mlx5/mlx5_rxtx_vec.c | 6 ++--\n drivers/net/mlx5/mlx5_stats.c | 9 +++---\n drivers/net/mlx5/mlx5_trigger.c | 2 +-\n 13 files changed, 66 insertions(+), 87 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex a2a9b9c1f98..0e68a13208b 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -527,11 +527,10 @@ mlx5_ibv_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,\n \n \tMLX5_ASSERT(ind_tbl);\n \tfor (i = 0; i != ind_tbl->queues_n; ++i) {\n-\t\tstruct mlx5_rxq_data *rxq = (*priv->rxqs)[ind_tbl->queues[i]];\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n-\t\t\t\tcontainer_of(rxq, struct mlx5_rxq_ctrl, rxq);\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev,\n+\t\t\t\t\t\t\t ind_tbl->queues[i]);\n \n-\t\twq[i] = rxq_ctrl->obj->wq;\n+\t\twq[i] = rxq->ctrl->obj->wq;\n \t}\n \tMLX5_ASSERT(i > 0);\n \t/* Finalise indirection table. */\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 749729d6fbe..6681b74c8f0 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1572,20 +1572,12 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \tmlx5_mp_os_req_stop_rxtx(dev);\n \t/* Free the eCPRI flex parser resource. */\n \tmlx5_flex_parser_ecpri_release(dev);\n-\tif (priv->rxqs != NULL) {\n+\tif (priv->rxq_privs != NULL) {\n \t\t/* XXX race condition if mlx5_rx_burst() is still running. */\n \t\trte_delay_us_sleep(1000);\n \t\tfor (i = 0; (i != priv->rxqs_n); ++i)\n \t\t\tmlx5_rxq_release(dev, i);\n \t\tpriv->rxqs_n = 0;\n-\t\tpriv->rxqs = NULL;\n-\t}\n-\tif (priv->representor) {\n-\t\t/* Each representor has a dedicated interrupts handler */\n-\t\tmlx5_free(dev->intr_handle);\n-\t\tdev->intr_handle = NULL;\n-\t}\n-\tif (priv->rxq_privs != NULL) {\n \t\tmlx5_free(priv->rxq_privs);\n \t\tpriv->rxq_privs = NULL;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex c674f5ba9c4..6a9c99a8826 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1406,7 +1406,6 @@ struct mlx5_priv {\n \tunsigned int rxqs_n; /* RX queues array size. */\n \tunsigned int txqs_n; /* TX queues array size. */\n \tstruct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */\n-\tstruct mlx5_rxq_data *(*rxqs)[]; /* (Shared) RX queues. */\n \tstruct mlx5_txq_data *(*txqs)[]; /* TX queues. */\n \tstruct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */\n \tstruct rte_eth_rss_conf rss_conf; /* RSS configuration. */\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex d219e255f0a..371ff387c99 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -682,15 +682,16 @@ mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,\n \n \t/* NULL queues designate drop queue. */\n \tif (ind_tbl->queues != NULL) {\n-\t\tstruct mlx5_rxq_data *rxq_data =\n-\t\t\t\t\t(*priv->rxqs)[ind_tbl->queues[0]];\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n-\t\t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n-\t\trxq_obj_type = rxq_ctrl->type;\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev,\n+\t\t\t\t\t\t\t ind_tbl->queues[0]);\n \n+\t\trxq_obj_type = rxq->ctrl->type;\n \t\t/* Enable TIR LRO only if all the queues were configured for. */\n \t\tfor (i = 0; i < ind_tbl->queues_n; ++i) {\n-\t\t\tif (!(*priv->rxqs)[ind_tbl->queues[i]]->lro) {\n+\t\t\tstruct mlx5_rxq_data *rxq_i =\n+\t\t\t\tmlx5_rxq_data_get(dev, ind_tbl->queues[i]);\n+\n+\t\t\tif (rxq_i != NULL && !rxq_i->lro) {\n \t\t\t\tlro = false;\n \t\t\t\tbreak;\n \t\t\t}\ndiff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c\nindex 7071a5f7039..16e96da8d24 100644\n--- a/drivers/net/mlx5/mlx5_ethdev.c\n+++ b/drivers/net/mlx5/mlx5_ethdev.c\n@@ -114,7 +114,6 @@ mlx5_dev_configure(struct rte_eth_dev *dev)\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n-\tpriv->rxqs = (void *)dev->data->rx_queues;\n \tpriv->txqs = (void *)dev->data->tx_queues;\n \tif (txqs_n != priv->txqs_n) {\n \t\tDRV_LOG(INFO, \"port %u Tx queues number update: %u -> %u\",\n@@ -171,11 +170,8 @@ mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev)\n \t\treturn -rte_errno;\n \t}\n \tfor (i = 0, j = 0; i < rxqs_n; i++) {\n-\t\tstruct mlx5_rxq_data *rxq_data;\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i);\n \n-\t\trxq_data = (*priv->rxqs)[i];\n-\t\trxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \t\tif (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)\n \t\t\trss_queue_arr[j++] = i;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex c10b9112593..49a74edd2e6 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -1166,10 +1166,11 @@ flow_drv_rxq_flags_set(struct rte_eth_dev *dev,\n \t\treturn;\n \tfor (i = 0; i != ind_tbl->queues_n; ++i) {\n \t\tint idx = ind_tbl->queues[i];\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n-\t\t\tcontainer_of((*priv->rxqs)[idx],\n-\t\t\t\t struct mlx5_rxq_ctrl, rxq);\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx);\n \n+\t\tMLX5_ASSERT(rxq_ctrl != NULL);\n+\t\tif (rxq_ctrl == NULL)\n+\t\t\tcontinue;\n \t\t/*\n \t\t * To support metadata register copy on Tx loopback,\n \t\t * this must be always enabled (metadata may arive\n@@ -1261,10 +1262,11 @@ flow_drv_rxq_flags_trim(struct rte_eth_dev *dev,\n \tMLX5_ASSERT(dev->data->dev_started);\n \tfor (i = 0; i != ind_tbl->queues_n; ++i) {\n \t\tint idx = ind_tbl->queues[i];\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n-\t\t\tcontainer_of((*priv->rxqs)[idx],\n-\t\t\t\t struct mlx5_rxq_ctrl, rxq);\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx);\n \n+\t\tMLX5_ASSERT(rxq_ctrl != NULL);\n+\t\tif (rxq_ctrl == NULL)\n+\t\t\tcontinue;\n \t\tif (priv->config.dv_flow_en &&\n \t\t priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&\n \t\t mlx5_flow_ext_mreg_supported(dev)) {\n@@ -1325,18 +1327,16 @@ flow_rxq_flags_clear(struct rte_eth_dev *dev)\n \tunsigned int i;\n \n \tfor (i = 0; i != priv->rxqs_n; ++i) {\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl;\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i);\n \t\tunsigned int j;\n \n-\t\tif (!(*priv->rxqs)[i])\n+\t\tif (rxq == NULL || rxq->ctrl == NULL)\n \t\t\tcontinue;\n-\t\trxq_ctrl = container_of((*priv->rxqs)[i],\n-\t\t\t\t\tstruct mlx5_rxq_ctrl, rxq);\n-\t\trxq_ctrl->flow_mark_n = 0;\n-\t\trxq_ctrl->rxq.mark = 0;\n+\t\trxq->ctrl->flow_mark_n = 0;\n+\t\trxq->ctrl->rxq.mark = 0;\n \t\tfor (j = 0; j != MLX5_FLOW_TUNNEL; ++j)\n-\t\t\trxq_ctrl->flow_tunnels_n[j] = 0;\n-\t\trxq_ctrl->rxq.tunnel = 0;\n+\t\t\trxq->ctrl->flow_tunnels_n[j] = 0;\n+\t\trxq->ctrl->rxq.tunnel = 0;\n \t}\n }\n \n@@ -1350,13 +1350,15 @@ void\n mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_data *data;\n \tunsigned int i;\n \n \tfor (i = 0; i != priv->rxqs_n; ++i) {\n-\t\tif (!(*priv->rxqs)[i])\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i);\n+\t\tstruct mlx5_rxq_data *data;\n+\n+\t\tif (rxq == NULL || rxq->ctrl == NULL)\n \t\t\tcontinue;\n-\t\tdata = (*priv->rxqs)[i];\n+\t\tdata = &rxq->ctrl->rxq;\n \t\tif (!rte_flow_dynf_metadata_avail()) {\n \t\t\tdata->dynf_meta = 0;\n \t\t\tdata->flow_meta_mask = 0;\n@@ -1547,7 +1549,7 @@ mlx5_flow_validate_action_queue(const struct rte_flow_action *action,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION_CONF,\n \t\t\t\t\t &queue->index,\n \t\t\t\t\t \"queue index out of range\");\n-\tif (!(*priv->rxqs)[queue->index])\n+\tif (mlx5_rxq_get(dev, queue->index) == NULL)\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION_CONF,\n \t\t\t\t\t &queue->index,\n@@ -1578,7 +1580,7 @@ mlx5_flow_validate_action_queue(const struct rte_flow_action *action,\n * 0 on success, a negative errno code on error.\n */\n static int\n-mlx5_validate_rss_queues(const struct rte_eth_dev *dev,\n+mlx5_validate_rss_queues(struct rte_eth_dev *dev,\n \t\t\t const uint16_t *queues, uint32_t queues_n,\n \t\t\t const char **error, uint32_t *queue_idx)\n {\n@@ -1594,13 +1596,12 @@ mlx5_validate_rss_queues(const struct rte_eth_dev *dev,\n \t\t\t*queue_idx = i;\n \t\t\treturn -EINVAL;\n \t\t}\n-\t\tif (!(*priv->rxqs)[queues[i]]) {\n+\t\trxq_ctrl = mlx5_rxq_ctrl_get(dev, queues[i]);\n+\t\tif (rxq_ctrl == NULL) {\n \t\t\t*error = \"queue is not configured\";\n \t\t\t*queue_idx = i;\n \t\t\treturn -EINVAL;\n \t\t}\n-\t\trxq_ctrl = container_of((*priv->rxqs)[queues[i]],\n-\t\t\t\t\tstruct mlx5_rxq_ctrl, rxq);\n \t\tif (i == 0)\n \t\t\trxq_type = rxq_ctrl->type;\n \t\tif (rxq_type != rxq_ctrl->type) {\ndiff --git a/drivers/net/mlx5/mlx5_rss.c b/drivers/net/mlx5/mlx5_rss.c\nindex c32129cdc2b..9ffc44b179f 100644\n--- a/drivers/net/mlx5/mlx5_rss.c\n+++ b/drivers/net/mlx5/mlx5_rss.c\n@@ -65,9 +65,11 @@ mlx5_rss_hash_update(struct rte_eth_dev *dev,\n \tpriv->rss_conf.rss_hf = rss_conf->rss_hf;\n \t/* Enable the RSS hash in all Rx queues. */\n \tfor (i = 0, idx = 0; idx != priv->rxqs_n; ++i) {\n-\t\tif (!(*priv->rxqs)[i])\n+\t\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i);\n+\n+\t\tif (rxq == NULL || rxq->ctrl == NULL)\n \t\t\tcontinue;\n-\t\t(*priv->rxqs)[i]->rss_hash = !!rss_conf->rss_hf &&\n+\t\trxq->ctrl->rxq.rss_hash = !!rss_conf->rss_hf &&\n \t\t\t!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS);\n \t\t++idx;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex 09de26c0d39..13fbd12b22c 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -148,10 +148,8 @@ void\n mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n \t\t struct rte_eth_rxq_info *qinfo)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl =\n-\t\tcontainer_of(rxq, struct mlx5_rxq_ctrl, rxq);\n+\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, rx_queue_id);\n+\tstruct mlx5_rxq_data *rxq = mlx5_rxq_data_get(dev, rx_queue_id);\n \n \tif (!rxq)\n \t\treturn;\n@@ -162,7 +160,7 @@ mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n \tqinfo->conf.rx_thresh.wthresh = 0;\n \tqinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;\n \tqinfo->conf.rx_drop_en = 1;\n-\tqinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;\n+\tqinfo->conf.rx_deferred_start = rxq_ctrl->obj == NULL ? 0 : 1;\n \tqinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;\n \tqinfo->scattered_rx = dev->data->scattered_rx;\n \tqinfo->nb_desc = mlx5_rxq_mprq_enabled(rxq) ?\n@@ -191,10 +189,8 @@ mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,\n \t\t struct rte_eth_burst_mode *mode)\n {\n \teth_rx_burst_t pkt_burst = dev->rx_pkt_burst;\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_data *rxq;\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, rx_queue_id);\n \n-\trxq = (*priv->rxqs)[rx_queue_id];\n \tif (!rxq) {\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n@@ -245,15 +241,13 @@ mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,\n uint32_t\n mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_data *rxq;\n+\tstruct mlx5_rxq_data *rxq = mlx5_rxq_data_get(dev, rx_queue_id);\n \n \tif (dev->rx_pkt_burst == NULL ||\n \t dev->rx_pkt_burst == removed_rx_burst) {\n \t\trte_errno = ENOTSUP;\n \t\treturn -rte_errno;\n \t}\n-\trxq = (*priv->rxqs)[rx_queue_id];\n \tif (!rxq) {\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex 25f7fc2071a..161399c764d 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -606,14 +606,13 @@ mlx5_mprq_enabled(struct rte_eth_dev *dev)\n \t\treturn 0;\n \t/* All the configured queues should be enabled. */\n \tfor (i = 0; i < priv->rxqs_n; ++i) {\n-\t\tstruct mlx5_rxq_data *rxq = (*priv->rxqs)[i];\n-\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = container_of\n-\t\t\t(rxq, struct mlx5_rxq_ctrl, rxq);\n+\t\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i);\n \n-\t\tif (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)\n+\t\tif (rxq_ctrl == NULL ||\n+\t\t rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)\n \t\t\tcontinue;\n \t\tn_ibv++;\n-\t\tif (mlx5_rxq_mprq_enabled(rxq))\n+\t\tif (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))\n \t\t\t++n;\n \t}\n \t/* Multi-Packet RQ can't be partially configured. */\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 98408da3c8e..cde01a48022 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -729,7 +729,7 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t}\n \tDRV_LOG(DEBUG, \"port %u adding Rx queue %u to list\",\n \t\tdev->data->port_id, idx);\n-\t(*priv->rxqs)[idx] = &rxq_ctrl->rxq;\n+\tdev->data->rx_queues[idx] = &rxq_ctrl->rxq;\n \treturn 0;\n }\n \n@@ -811,7 +811,7 @@ mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,\n \t}\n \tDRV_LOG(DEBUG, \"port %u adding hairpin Rx queue %u to list\",\n \t\tdev->data->port_id, idx);\n-\t(*priv->rxqs)[idx] = &rxq_ctrl->rxq;\n+\tdev->data->rx_queues[idx] = &rxq_ctrl->rxq;\n \treturn 0;\n }\n \n@@ -1712,8 +1712,7 @@ mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \n-\tif (priv->rxq_privs == NULL)\n-\t\treturn NULL;\n+\tMLX5_ASSERT(priv->rxq_privs != NULL);\n \treturn (*priv->rxq_privs)[idx];\n }\n \n@@ -1799,7 +1798,7 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)\n \t\tLIST_REMOVE(rxq, owner_entry);\n \t\tLIST_REMOVE(rxq_ctrl, next);\n \t\tmlx5_free(rxq_ctrl);\n-\t\t(*priv->rxqs)[idx] = NULL;\n+\t\tdev->data->rx_queues[idx] = NULL;\n \t\tmlx5_free(rxq);\n \t\t(*priv->rxq_privs)[idx] = NULL;\n \t}\n@@ -1845,14 +1844,10 @@ enum mlx5_rxq_type\n mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl = NULL;\n+\tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx);\n \n-\tif (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {\n-\t\trxq_ctrl = container_of((*priv->rxqs)[idx],\n-\t\t\t\t\tstruct mlx5_rxq_ctrl,\n-\t\t\t\t\trxq);\n+\tif (idx < priv->rxqs_n && rxq_ctrl != NULL)\n \t\treturn rxq_ctrl->type;\n-\t}\n \treturn MLX5_RXQ_TYPE_UNDEFINED;\n }\n \n@@ -2619,13 +2614,13 @@ mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n-\tstruct mlx5_rxq_data *data;\n \tunsigned int i;\n \n \tfor (i = 0; i != priv->rxqs_n; ++i) {\n-\t\tif (!(*priv->rxqs)[i])\n+\t\tstruct mlx5_rxq_data *data = mlx5_rxq_data_get(dev, i);\n+\n+\t\tif (data == NULL)\n \t\t\tcontinue;\n-\t\tdata = (*priv->rxqs)[i];\n \t\tdata->sh = sh;\n \t\tdata->rt_timestamp = priv->config.rt_timestamp;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c\nindex 511681841ca..6212ce8247d 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec.c\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec.c\n@@ -578,11 +578,11 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev)\n \t\treturn -ENOTSUP;\n \t/* All the configured queues should support. */\n \tfor (i = 0; i < priv->rxqs_n; ++i) {\n-\t\tstruct mlx5_rxq_data *rxq = (*priv->rxqs)[i];\n+\t\tstruct mlx5_rxq_data *rxq_data = mlx5_rxq_data_get(dev, i);\n \n-\t\tif (!rxq)\n+\t\tif (!rxq_data)\n \t\t\tcontinue;\n-\t\tif (mlx5_rxq_check_vec_support(rxq) < 0)\n+\t\tif (mlx5_rxq_check_vec_support(rxq_data) < 0)\n \t\t\tbreak;\n \t}\n \tif (i != priv->rxqs_n)\ndiff --git a/drivers/net/mlx5/mlx5_stats.c b/drivers/net/mlx5/mlx5_stats.c\nindex ae2f5668a74..732775954ad 100644\n--- a/drivers/net/mlx5/mlx5_stats.c\n+++ b/drivers/net/mlx5/mlx5_stats.c\n@@ -107,7 +107,7 @@ mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n \tmemset(&tmp, 0, sizeof(tmp));\n \t/* Add software counters. */\n \tfor (i = 0; (i != priv->rxqs_n); ++i) {\n-\t\tstruct mlx5_rxq_data *rxq = (*priv->rxqs)[i];\n+\t\tstruct mlx5_rxq_data *rxq = mlx5_rxq_data_get(dev, i);\n \n \t\tif (rxq == NULL)\n \t\t\tcontinue;\n@@ -181,10 +181,11 @@ mlx5_stats_reset(struct rte_eth_dev *dev)\n \tunsigned int i;\n \n \tfor (i = 0; (i != priv->rxqs_n); ++i) {\n-\t\tif ((*priv->rxqs)[i] == NULL)\n+\t\tstruct mlx5_rxq_data *rxq_data = mlx5_rxq_data_get(dev, i);\n+\n+\t\tif (rxq_data == NULL)\n \t\t\tcontinue;\n-\t\tmemset(&(*priv->rxqs)[i]->stats, 0,\n-\t\t sizeof(struct mlx5_rxq_stats));\n+\t\tmemset(&rxq_data->stats, 0, sizeof(struct mlx5_rxq_stats));\n \t}\n \tfor (i = 0; (i != priv->txqs_n); ++i) {\n \t\tif ((*priv->txqs)[i] == NULL)\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex b3188f510fb..1e865e74e39 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -176,7 +176,7 @@ mlx5_rxq_start(struct rte_eth_dev *dev)\n \t\tif (!rxq_ctrl->obj) {\n \t\t\tDRV_LOG(ERR,\n \t\t\t\t\"Port %u Rx queue %u can't allocate resources.\",\n-\t\t\t\tdev->data->port_id, (*priv->rxqs)[i]->idx);\n+\t\t\t\tdev->data->port_id, i);\n \t\t\trte_errno = ENOMEM;\n \t\t\tgoto error;\n \t\t}\n", "prefixes": [ "10/11" ] }