diff mbox series

[v2] net/mlx5: fix metadata item endianness conversion

Message ID 1579273172-19188-1-git-send-email-viacheslavo@mellanox.com (mailing list archive)
State Accepted, archived
Delegated to: Ferruh Yigit
Headers
Series [v2] net/mlx5: fix metadata item endianness conversion |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-testing fail Testing issues
ci/iol-nxp-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/travis-robot success Travis build: passed
ci/Intel-compilation success Compilation OK

Commit Message

Slava Ovsiienko Jan. 17, 2020, 2:59 p.m. UTC 
  The mlx5 datapath does not implement any endianness conversions
for the metadata being sent and received to provide the better
performance (because these conversions would be performed for
each packet). These metadata are also involved into flow processing
(there might be some flows matching on metadata patterns or setting
the new metadata values) inside the NIC. It order to configure
hardware in correct way all necessary endianness conversions are
done by rte_flow handling code (only once on flow creation). This
patch fixes one of these conversions for the little-endian hosts
in case if META/MARK items are less than 32 bits.

Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
---
v1: - http://patchwork.dpdk.org/patch/64125/
v2: - commit message is rewritten

 drivers/net/mlx5/mlx5_flow_dv.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Comments

Ferruh Yigit Jan. 17, 2020, 5:19 p.m. UTC | #1 
On 1/17/2020 2:59 PM, Viacheslav Ovsiienko wrote:
> The mlx5 datapath does not implement any endianness conversions
> for the metadata being sent and received to provide the better
> performance (because these conversions would be performed for
> each packet). These metadata are also involved into flow processing
> (there might be some flows matching on metadata patterns or setting
> the new metadata values) inside the NIC. It order to configure
> hardware in correct way all necessary endianness conversions are
> done by rte_flow handling code (only once on flow creation). This
> patch fixes one of these conversions for the little-endian hosts
> in case if META/MARK items are less than 32 bits.
> 
> Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> Acked-by: Matan Azrad <matan@mellanox.com>
> ---
> v1: - http://patchwork.dpdk.org/patch/64125/
> v2: - commit message is rewritten
> 

Applied to dpdk-next-net/master, thanks.
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index dd21bc6..e8a764c 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -5909,8 +5909,12 @@  struct field_modify_info modify_tcp[] = {
 			struct mlx5_priv *priv = dev->data->dev_private;
 			uint32_t msk_c0 = priv->sh->dv_regc0_mask;
 			uint32_t shl_c0 = rte_bsf32(msk_c0);
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+			uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
 
-			msk_c0 = rte_cpu_to_be_32(msk_c0);
+			value >>= shr_c0;
+			mask >>= shr_c0;
+#endif
 			value <<= shl_c0;
 			mask <<= shl_c0;
 			assert(msk_c0);