[v3,1/3] bus/pci: enable PCI master in command register
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Commit Message
This adds the support to set 'Bus Master Enable' bit in the PCI command
register.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Tested-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/bus/pci/pci_common.c | 20 ++++++++++++++++++++
drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++
drivers/bus/pci/version.map | 3 +++
lib/pci/rte_pci.h | 4 ++++
4 files changed, 39 insertions(+)
Comments
On 23/04/2021 12:39, Haiyue Wang wrote:
> This adds the support to set 'Bus Master Enable' bit in the PCI command
> register.
>
> Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
> Tested-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/bus/pci/pci_common.c | 20 ++++++++++++++++++++
> drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++
> drivers/bus/pci/version.map | 3 +++
> lib/pci/rte_pci.h | 4 ++++
> 4 files changed, 39 insertions(+)
>
> diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
> index ee7f96635..b631cb9c7 100644
> --- a/drivers/bus/pci/pci_common.c
> +++ b/drivers/bus/pci/pci_common.c
> @@ -746,6 +746,26 @@ rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap)
> return 0;
> }
>
> +int
> +rte_pci_enable_bus_master(struct rte_pci_device *dev)
> +{
> + uint16_t cmd;
> +
> + if (rte_pci_read_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
> + RTE_LOG(ERR, EAL, "error in reading PCI command register\n");
> + return -1;
> + }
> +
> + cmd |= RTE_PCI_COMMAND_MASTER;
> +
> + if (rte_pci_write_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
> + RTE_LOG(ERR, EAL, "error in writing PCI command register\n");
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> struct rte_pci_bus rte_pci_bus = {
> .bus = {
> .scan = rte_pci_scan,
> diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
> index 64886b473..83caf477b 100644
> --- a/drivers/bus/pci/rte_bus_pci.h
> +++ b/drivers/bus/pci/rte_bus_pci.h
> @@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f);
> __rte_experimental
> off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
>
> +/**
> + * Enables Bus Master for device's PCI command register.
> + *
> + * @param dev
> + * A pointer to rte_pci_device structure.
> + *
> + * @return
> + * 0 on success, -1 on error in PCI config space read/write.
> + */
> +__rte_experimental
> +int rte_pci_enable_bus_master(struct rte_pci_device *dev);
> +
> /**
> * Register a PCI driver.
> *
> diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map
> index f33ed0abd..9dbec12a0 100644
> --- a/drivers/bus/pci/version.map
> +++ b/drivers/bus/pci/version.map
> @@ -21,4 +21,7 @@ EXPERIMENTAL {
> global:
>
> rte_pci_find_ext_capability;
> +
> + # added in 21.05
> + rte_pci_enable_bus_master;
> };
> diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
> index a8f8e404a..1f33d687f 100644
> --- a/lib/pci/rte_pci.h
> +++ b/lib/pci/rte_pci.h
> @@ -32,6 +32,10 @@ extern "C" {
>
> #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
> #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
> +#define RTE_PCI_COMMAND 0x04 /* 16 bits */
> +
> +/* PCI Command Register */
> +#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */
>
> /* PCI Express capability registers */
> #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */
>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
On Fri, Apr 23, 2021 at 2:06 PM Haiyue Wang <haiyue.wang@intel.com> wrote:
> diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
> index 64886b473..83caf477b 100644
> --- a/drivers/bus/pci/rte_bus_pci.h
> +++ b/drivers/bus/pci/rte_bus_pci.h
> @@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f);
> __rte_experimental
> off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
>
> +/**
> + * Enables Bus Master for device's PCI command register.
> + *
> + * @param dev
> + * A pointer to rte_pci_device structure.
> + *
> + * @return
> + * 0 on success, -1 on error in PCI config space read/write.
> + */
> +__rte_experimental
> +int rte_pci_enable_bus_master(struct rte_pci_device *dev);
I can see pci/vfio and net/hns3 has a similar helper to enable *and*
disable bus master.
I'd rather go with a "set" helper, and then we can clean existing
drivers who had their own helper:
drivers/bus/pci/linux/pci_uio.c
drivers/bus/pci/linux/pci_vfio.c
drivers/net/hns3/hns3_ethdev_vf.c
> +
> /**
> * Register a PCI driver.
> *
> diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map
> index f33ed0abd..9dbec12a0 100644
> --- a/drivers/bus/pci/version.map
> +++ b/drivers/bus/pci/version.map
> @@ -21,4 +21,7 @@ EXPERIMENTAL {
> global:
>
> rte_pci_find_ext_capability;
> +
> + # added in 21.05
> + rte_pci_enable_bus_master;
> };
> diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
> index a8f8e404a..1f33d687f 100644
> --- a/lib/pci/rte_pci.h
> +++ b/lib/pci/rte_pci.h
> @@ -32,6 +32,10 @@ extern "C" {
>
> #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
> #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
> +#define RTE_PCI_COMMAND 0x04 /* 16 bits */
This file uses tab for indent.
> +
> +/* PCI Command Register */
> +#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */
>
> /* PCI Express capability registers */
> #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */
> --
> 2.31.1
>
> -----Original Message-----
> From: David Marchand <david.marchand@redhat.com>
> Sent: Tuesday, April 27, 2021 17:29
> To: Wang, Haiyue <haiyue.wang@intel.com>; Gaetan Rivet <grive@u256.net>
> Cc: dev <dev@dpdk.org>; Zhang, Qi Z <qi.z.zhang@intel.com>; Wang, Liang-min <liang-min.wang@intel.com>;
> Ray Kinsella <mdr@ashroe.eu>; Neil Horman <nhorman@tuxdriver.com>
> Subject: Re: [dpdk-dev] [PATCH v3 1/3] bus/pci: enable PCI master in command register
>
> On Fri, Apr 23, 2021 at 2:06 PM Haiyue Wang <haiyue.wang@intel.com> wrote:
> > diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
> > index 64886b473..83caf477b 100644
> > --- a/drivers/bus/pci/rte_bus_pci.h
> > +++ b/drivers/bus/pci/rte_bus_pci.h
> > @@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f);
> > __rte_experimental
> > off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
> >
> > +/**
> > + * Enables Bus Master for device's PCI command register.
> > + *
> > + * @param dev
> > + * A pointer to rte_pci_device structure.
> > + *
> > + * @return
> > + * 0 on success, -1 on error in PCI config space read/write.
> > + */
> > +__rte_experimental
> > +int rte_pci_enable_bus_master(struct rte_pci_device *dev);
>
> I can see pci/vfio and net/hns3 has a similar helper to enable *and*
> disable bus master.
>
> I'd rather go with a "set" helper, and then we can clean existing
> drivers who had their own helper:
> drivers/bus/pci/linux/pci_uio.c
> drivers/bus/pci/linux/pci_vfio.c
> drivers/net/hns3/hns3_ethdev_vf.c
>
>
Got it, will change it to 'set'.
> > +
> > /**
> > * Register a PCI driver.
> > *
> > diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map
> > index f33ed0abd..9dbec12a0 100644
> > --- a/drivers/bus/pci/version.map
> > +++ b/drivers/bus/pci/version.map
> > @@ -21,4 +21,7 @@ EXPERIMENTAL {
> > global:
> >
> > rte_pci_find_ext_capability;
> > +
> > + # added in 21.05
> > + rte_pci_enable_bus_master;
> > };
> > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
> > index a8f8e404a..1f33d687f 100644
> > --- a/lib/pci/rte_pci.h
> > +++ b/lib/pci/rte_pci.h
> > @@ -32,6 +32,10 @@ extern "C" {
> >
> > #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
> > #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
> > +#define RTE_PCI_COMMAND 0x04 /* 16 bits */
>
> This file uses tab for indent.
>
Yes, I use two tabs, then the vi editor shows that they are aligned.
but the patch doesn't show well.
So use one tab ?
>
> > +
> > +/* PCI Command Register */
> > +#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */
> >
> > /* PCI Express capability registers */
> > #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */
> > --
> > 2.31.1
> >
>
>
> --
> David Marchand
On Tue, Apr 27, 2021 at 3:35 PM Wang, Haiyue <haiyue.wang@intel.com> wrote:
> > > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
> > > index a8f8e404a..1f33d687f 100644
> > > --- a/lib/pci/rte_pci.h
> > > +++ b/lib/pci/rte_pci.h
> > > @@ -32,6 +32,10 @@ extern "C" {
> > >
> > > #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
> > > #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
> > > +#define RTE_PCI_COMMAND 0x04 /* 16 bits */
> >
> > This file uses tab for indent.
> >
>
> Yes, I use two tabs, then the vi editor shows that they are aligned.
> but the patch doesn't show well.
>
> So use one tab ?
Sorry, your patch was good.
You can discard this comment.
@@ -746,6 +746,26 @@ rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap)
return 0;
}
+int
+rte_pci_enable_bus_master(struct rte_pci_device *dev)
+{
+ uint16_t cmd;
+
+ if (rte_pci_read_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in reading PCI command register\n");
+ return -1;
+ }
+
+ cmd |= RTE_PCI_COMMAND_MASTER;
+
+ if (rte_pci_write_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in writing PCI command register\n");
+ return -1;
+ }
+
+ return 0;
+}
+
struct rte_pci_bus rte_pci_bus = {
.bus = {
.scan = rte_pci_scan,
@@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f);
__rte_experimental
off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
+/**
+ * Enables Bus Master for device's PCI command register.
+ *
+ * @param dev
+ * A pointer to rte_pci_device structure.
+ *
+ * @return
+ * 0 on success, -1 on error in PCI config space read/write.
+ */
+__rte_experimental
+int rte_pci_enable_bus_master(struct rte_pci_device *dev);
+
/**
* Register a PCI driver.
*
@@ -21,4 +21,7 @@ EXPERIMENTAL {
global:
rte_pci_find_ext_capability;
+
+ # added in 21.05
+ rte_pci_enable_bus_master;
};
@@ -32,6 +32,10 @@ extern "C" {
#define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
#define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
+#define RTE_PCI_COMMAND 0x04 /* 16 bits */
+
+/* PCI Command Register */
+#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */
/* PCI Express capability registers */
#define RTE_PCI_EXP_DEVCTL 8 /* Device Control */