[1/4] net/dpaa2: update mc to 10.32

Message ID 20220422045729.3320637-1-g.singh@nxp.com (mailing list archive)
State Accepted, archived
Delegated to: Ferruh Yigit
Headers
Series [1/4] net/dpaa2: update mc to 10.32 |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Gagandeep Singh April 22, 2022, 4:57 a.m. UTC
  From: Rohit Raj <rohit.raj@nxp.com>

Updating the management complex to version 10.32

Signed-off-by: Rohit Raj <rohit.raj@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
---
 drivers/bus/fslmc/mc/fsl_dpmng.h    |  4 ++--
 drivers/net/dpaa2/mc/dpni.c         |  6 ++++--
 drivers/net/dpaa2/mc/fsl_dpni.h     |  1 +
 drivers/net/dpaa2/mc/fsl_dpni_cmd.h | 26 +++++++++++++++-----------
 4 files changed, 22 insertions(+), 15 deletions(-)
  

Comments

Ferruh Yigit May 10, 2022, 12:51 p.m. UTC | #1
On 4/22/2022 5:57 AM, Gagandeep Singh wrote:
> From: Rohit Raj <rohit.raj@nxp.com>
> 
> Updating the management complex to version 10.32
> 
> Signed-off-by: Rohit Raj <rohit.raj@nxp.com>
> Signed-off-by: Gagandeep Singh <g.singh@nxp.com>

Hi Hemant, Sachin,

The set looks good to me, do you have any comment/review?
  
Hemant Agrawal May 10, 2022, 12:53 p.m. UTC | #2
Hi Ferruh,
	I am ok for it. 
You can add:
Acked-by:  Hemant Agrawal <hemant.agrawal@nxp.com>

> -----Original Message-----
> From: Ferruh Yigit <ferruh.yigit@xilinx.com>
> Sent: Tuesday, May 10, 2022 6:22 PM
> To: Gagandeep Singh <G.Singh@nxp.com>; dev@dpdk.org; Hemant Agrawal
> <hemant.agrawal@nxp.com>; Sachin Saxena (OSS)
> <sachin.saxena@oss.nxp.com>
> Cc: Rohit Raj <rohit.raj@nxp.com>
> Subject: Re: [PATCH 1/4] net/dpaa2: update mc to 10.32
> Importance: High
> 
> On 4/22/2022 5:57 AM, Gagandeep Singh wrote:
> > From: Rohit Raj <rohit.raj@nxp.com>
> >
> > Updating the management complex to version 10.32
> >
> > Signed-off-by: Rohit Raj <rohit.raj@nxp.com>
> > Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
> 
> Hi Hemant, Sachin,
> 
> The set looks good to me, do you have any comment/review?
  
Ferruh Yigit May 10, 2022, 4:33 p.m. UTC | #3
On 4/22/2022 5:57 AM, Gagandeep Singh wrote:
> From: Rohit Raj <rohit.raj@nxp.com>
> 
> Updating the management complex to version 10.32
> 
> Signed-off-by: Rohit Raj <rohit.raj@nxp.com>
> Signed-off-by: Gagandeep Singh <g.singh@nxp.com>

For series,
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>

Series applied to dpdk-next-net/main, thanks.
  

Patch

diff --git a/drivers/bus/fslmc/mc/fsl_dpmng.h b/drivers/bus/fslmc/mc/fsl_dpmng.h
index 073d47efbf..c6ea220df7 100644
--- a/drivers/bus/fslmc/mc/fsl_dpmng.h
+++ b/drivers/bus/fslmc/mc/fsl_dpmng.h
@@ -1,7 +1,7 @@ 
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2015 Freescale Semiconductor Inc.
- * Copyright 2017-2021 NXP
+ * Copyright 2017-2022 NXP
  *
  */
 #ifndef __FSL_DPMNG_H
@@ -20,7 +20,7 @@  struct fsl_mc_io;
  * Management Complex firmware version information
  */
 #define MC_VER_MAJOR 10
-#define MC_VER_MINOR 29
+#define MC_VER_MINOR 32
 
 /**
  * struct mc_version
diff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c
index c5cc9302f9..4d97b98939 100644
--- a/drivers/net/dpaa2/mc/dpni.c
+++ b/drivers/net/dpaa2/mc/dpni.c
@@ -1,7 +1,7 @@ 
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  *
  */
 #include <fsl_mc_sys.h>
@@ -596,6 +596,7 @@  int dpni_get_attributes(struct fsl_mc_io *mc_io,
 	attr->num_channels = rsp_params->num_channels;
 	attr->qos_entries = rsp_params->qos_entries;
 	attr->fs_entries = le16_to_cpu(rsp_params->fs_entries);
+	attr->num_opr = le16_to_cpu(rsp_params->num_opr);
 	attr->qos_key_size = rsp_params->qos_key_size;
 	attr->fs_key_size = rsp_params->fs_key_size;
 	attr->wriop_version = le16_to_cpu(rsp_params->wriop_version);
@@ -2238,7 +2239,8 @@  int dpni_get_early_drop(struct fsl_mc_io *mc_io,
  * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
  * @token:	Token of DPNI object
  * @qtype:	Type of queue - Rx, Tx and Tx confirm types are supported
- * @tc_id:	Traffic class selection (0-7)
+ * @param:	Traffic class and channel. Bits[0-7] contain traaffic class,
+ *		bite[8-15] contains channel id
  * @cfg:	congestion notification configuration
  *
  * Return:	'0' on Success; error code otherwise.
diff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h
index e970e4702a..ce84f4265e 100644
--- a/drivers/net/dpaa2/mc/fsl_dpni.h
+++ b/drivers/net/dpaa2/mc/fsl_dpni.h
@@ -372,6 +372,7 @@  struct dpni_attr {
 	uint8_t  vlan_filter_entries;
 	uint8_t  qos_entries;
 	uint16_t fs_entries;
+	uint16_t num_opr;
 	uint8_t  qos_key_size;
 	uint8_t  fs_key_size;
 	uint16_t wriop_version;
diff --git a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
index b7bd7556af..781f936add 100644
--- a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
+++ b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h
@@ -1,7 +1,7 @@ 
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
  * Copyright 2013-2016 Freescale Semiconductor Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2022 NXP
  *
  */
 #ifndef _FSL_DPNI_CMD_H
@@ -9,7 +9,7 @@ 
 
 /* DPNI Version */
 #define DPNI_VER_MAJOR				8
-#define DPNI_VER_MINOR				0
+#define DPNI_VER_MINOR				2
 
 #define DPNI_CMD_BASE_VERSION			1
 #define DPNI_CMD_VERSION_2			2
@@ -17,6 +17,7 @@ 
 #define DPNI_CMD_VERSION_4			4
 #define DPNI_CMD_VERSION_5			5
 #define DPNI_CMD_VERSION_6			6
+#define DPNI_CMD_VERSION_7			7
 #define DPNI_CMD_ID_OFFSET			4
 
 #define DPNI_CMD(id)	(((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION)
@@ -25,17 +26,18 @@ 
 #define DPNI_CMD_V4(id)	(((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_4)
 #define DPNI_CMD_V5(id)	(((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_5)
 #define DPNI_CMD_V6(id)	(((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_6)
+#define DPNI_CMD_V7(id)	(((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_VERSION_7)
 
 /* Command IDs */
 #define DPNI_CMDID_OPEN				DPNI_CMD(0x801)
 #define DPNI_CMDID_CLOSE			DPNI_CMD(0x800)
-#define DPNI_CMDID_CREATE			DPNI_CMD_V6(0x901)
+#define DPNI_CMDID_CREATE			DPNI_CMD_V7(0x901)
 #define DPNI_CMDID_DESTROY			DPNI_CMD(0x981)
 #define DPNI_CMDID_GET_API_VERSION		DPNI_CMD(0xa01)
 
 #define DPNI_CMDID_ENABLE			DPNI_CMD(0x002)
 #define DPNI_CMDID_DISABLE			DPNI_CMD(0x003)
-#define DPNI_CMDID_GET_ATTR			DPNI_CMD_V4(0x004)
+#define DPNI_CMDID_GET_ATTR			DPNI_CMD_V6(0x004)
 #define DPNI_CMDID_RESET			DPNI_CMD(0x005)
 #define DPNI_CMDID_IS_ENABLED			DPNI_CMD(0x006)
 
@@ -104,17 +106,17 @@ 
 #define DPNI_CMDID_GET_CONGESTION_NOTIFICATION	DPNI_CMD_V3(0x268)
 #define DPNI_CMDID_SET_EARLY_DROP		DPNI_CMD_V3(0x269)
 #define DPNI_CMDID_GET_EARLY_DROP		DPNI_CMD_V3(0x26A)
-#define DPNI_CMDID_GET_OFFLOAD			DPNI_CMD(0x26B)
-#define DPNI_CMDID_SET_OFFLOAD			DPNI_CMD(0x26C)
+#define DPNI_CMDID_GET_OFFLOAD			DPNI_CMD_V2(0x26B)
+#define DPNI_CMDID_SET_OFFLOAD			DPNI_CMD_V2(0x26C)
 #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE	DPNI_CMD(0x266)
 #define DPNI_CMDID_GET_TX_CONFIRMATION_MODE	DPNI_CMD(0x26D)
-#define DPNI_CMDID_SET_OPR			DPNI_CMD(0x26e)
-#define DPNI_CMDID_GET_OPR			DPNI_CMD(0x26f)
+#define DPNI_CMDID_SET_OPR			DPNI_CMD_V2(0x26e)
+#define DPNI_CMDID_GET_OPR			DPNI_CMD_V2(0x26f)
 #define DPNI_CMDID_LOAD_SW_SEQUENCE		DPNI_CMD(0x270)
 #define DPNI_CMDID_ENABLE_SW_SEQUENCE		DPNI_CMD(0x271)
 #define DPNI_CMDID_GET_SW_SEQUENCE_LAYOUT	DPNI_CMD(0x272)
-#define DPNI_CMDID_SET_RX_FS_DIST		DPNI_CMD(0x273)
-#define DPNI_CMDID_SET_RX_HASH_DIST		DPNI_CMD(0x274)
+#define DPNI_CMDID_SET_RX_FS_DIST		DPNI_CMD_V2(0x273)
+#define DPNI_CMDID_SET_RX_HASH_DIST		DPNI_CMD_V2(0x274)
 #define DPNI_CMDID_ADD_CUSTOM_TPID		DPNI_CMD(0x275)
 #define DPNI_CMDID_REMOVE_CUSTOM_TPID		DPNI_CMD(0x276)
 #define DPNI_CMDID_GET_CUSTOM_TPID		DPNI_CMD(0x277)
@@ -238,7 +240,7 @@  struct dpni_rsp_get_attr {
 	uint8_t qos_entries;
 	uint8_t pad2;
 	uint16_t fs_entries;
-	uint16_t pad3;
+	uint16_t num_opr;
 	/* response word 2 */
 	uint8_t qos_key_size;
 	uint8_t fs_key_size;
@@ -906,6 +908,8 @@  struct dpni_rsp_single_step_cfg {
 	uint16_t	flags;
 	uint16_t	offset;
 	uint32_t	peer_delay;
+	uint32_t	ptp_onestep_reg_base;
+	uint32_t	pad0;
 };
 
 #define DPNI_PORT_LOOPBACK_EN_SHIFT	0