[v2,10/37] baseband/acc100: avoid mux for small inbound frames
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Commit Message
Update check_mux to avoid multiplexing small inbound frames.
Preventing to multiplex code blocks when K < 512B per specs.
Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
drivers/baseband/acc100/acc100_pmd.h | 1 +
drivers/baseband/acc100/rte_acc100_pmd.c | 16 +++++++++++-----
2 files changed, 12 insertions(+), 5 deletions(-)
Comments
On 8/20/22 04:31, Hernan Vargas wrote:
> Update check_mux to avoid multiplexing small inbound frames.
> Preventing to multiplex code blocks when K < 512B per specs.
It looks like a fix, and so should Fixes tag be added an stable cc'ed.
> Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
> ---
> drivers/baseband/acc100/acc100_pmd.h | 1 +
> drivers/baseband/acc100/rte_acc100_pmd.c | 16 +++++++++++-----
> 2 files changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h
> index 0c9810ca56..19a1f434bc 100644
> --- a/drivers/baseband/acc100/acc100_pmd.h
> +++ b/drivers/baseband/acc100/acc100_pmd.h
> @@ -135,6 +135,7 @@
> #define ACC100_DEC_OFFSET (80)
> #define ACC100_EXT_MEM /* Default option with memory external to CPU */
> #define ACC100_HARQ_OFFSET_THRESHOLD 1024
> +#define ACC100_LIMIT_DL_MUX_BITS 534
>
> /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
> #define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index 5d09908fd0..71409e11a1 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -3548,20 +3548,25 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data,
> }
>
> /* Check we can mux encode operations with common FCW */
> -static inline bool
> +static inline int16_t
> check_mux(struct rte_bbdev_enc_op **ops, uint16_t num) {
> uint16_t i;
> if (num <= 1)
> - return false;
> + return 1;
> for (i = 1; i < num; ++i) {
> /* Only mux compatible code blocks */
> if (memcmp((uint8_t *)(&ops[i]->ldpc_enc) + ACC100_ENC_OFFSET,
> (uint8_t *)(&ops[0]->ldpc_enc) +
> ACC100_ENC_OFFSET,
> ACC100_CMP_ENC_SIZE) != 0)
> - return false;
> + return i;
> }
> - return true;
> + /* Avoid multiplexing small inbound size frames */
> + int Kp = (ops[0]->ldpc_enc.basegraph == 1 ? 22 : 10) *
> + ops[0]->ldpc_enc.z_c - ops[0]->ldpc_enc.n_filler;
> + if (Kp <= ACC100_LIMIT_DL_MUX_BITS)
> + return 1;
> + return num;
> }
>
> /** Enqueue encode operations for ACC100 device in CB mode. */
> @@ -3583,7 +3588,8 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data,
> }
> avail--;
> enq = RTE_MIN(left, ACC100_MUX_5GDL_DESC);
> - if (check_mux(&ops[i], enq)) {
> + enq = check_mux(&ops[i], enq);
> + if (enq > 1) {
> ret = enqueue_ldpc_enc_n_op_cb(q, &ops[i],
> desc_idx, enq);
> if (ret < 0) {
@@ -135,6 +135,7 @@
#define ACC100_DEC_OFFSET (80)
#define ACC100_EXT_MEM /* Default option with memory external to CPU */
#define ACC100_HARQ_OFFSET_THRESHOLD 1024
+#define ACC100_LIMIT_DL_MUX_BITS 534
/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
#define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */
@@ -3548,20 +3548,25 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data,
}
/* Check we can mux encode operations with common FCW */
-static inline bool
+static inline int16_t
check_mux(struct rte_bbdev_enc_op **ops, uint16_t num) {
uint16_t i;
if (num <= 1)
- return false;
+ return 1;
for (i = 1; i < num; ++i) {
/* Only mux compatible code blocks */
if (memcmp((uint8_t *)(&ops[i]->ldpc_enc) + ACC100_ENC_OFFSET,
(uint8_t *)(&ops[0]->ldpc_enc) +
ACC100_ENC_OFFSET,
ACC100_CMP_ENC_SIZE) != 0)
- return false;
+ return i;
}
- return true;
+ /* Avoid multiplexing small inbound size frames */
+ int Kp = (ops[0]->ldpc_enc.basegraph == 1 ? 22 : 10) *
+ ops[0]->ldpc_enc.z_c - ops[0]->ldpc_enc.n_filler;
+ if (Kp <= ACC100_LIMIT_DL_MUX_BITS)
+ return 1;
+ return num;
}
/** Enqueue encode operations for ACC100 device in CB mode. */
@@ -3583,7 +3588,8 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data,
}
avail--;
enq = RTE_MIN(left, ACC100_MUX_5GDL_DESC);
- if (check_mux(&ops[i], enq)) {
+ enq = check_mux(&ops[i], enq);
+ if (enq > 1) {
ret = enqueue_ldpc_enc_n_op_cb(q, &ops[i],
desc_idx, enq);
if (ret < 0) {