[v4,4/6] net/i40e: avoid using const variable in assertion
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Commit Message
Clang does not allow const variable in a static_assert
expression.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
drivers/net/i40e/i40e_ethdev.h | 1 +
drivers/net/i40e/i40e_rxtx_vec_sse.c | 10 ++++------
2 files changed, 5 insertions(+), 6 deletions(-)
Comments
On Wed, Jan 17, 2024 at 10:19:58AM -0800, Stephen Hemminger wrote:
> Clang does not allow const variable in a static_assert
> expression.
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
> Clang does not allow const variable in a static_assert
> expression.
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
> ---
> drivers/net/i40e/i40e_ethdev.h | 1 +
> drivers/net/i40e/i40e_rxtx_vec_sse.c | 10 ++++------
> 2 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
> index 1bbe7ad37600..445e1c0b381f 100644
> --- a/drivers/net/i40e/i40e_ethdev.h
> +++ b/drivers/net/i40e/i40e_ethdev.h
> @@ -278,6 +278,7 @@ enum i40e_flxpld_layer_idx {
> #define I40E_DEFAULT_DCB_APP_PRIO 3
>
> #define I40E_FDIR_PRG_PKT_CNT 128
> +#define I40E_FDIR_ID_BIT_SHIFT 13
>
> /*
> * Struct to store flow created.
> diff --git a/drivers/net/i40e/i40e_rxtx_vec_sse.c b/drivers/net/i40e/i40e_rxtx_vec_sse.c
> index 9200a23ff662..2d4480a7651b 100644
> --- a/drivers/net/i40e/i40e_rxtx_vec_sse.c
> +++ b/drivers/net/i40e/i40e_rxtx_vec_sse.c
> @@ -143,10 +143,9 @@ descs_to_fdir_32b(volatile union i40e_rx_desc *rxdp, struct rte_mbuf **rx_pkt)
> /* convert fdir_id_mask into a single bit, then shift as required for
> * correct location in the mbuf->olflags
> */
> - const uint32_t FDIR_ID_BIT_SHIFT = 13;
> - RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << FDIR_ID_BIT_SHIFT));
> + RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << I40E_FDIR_ID_BIT_SHIFT));
> v_fd_id_mask = _mm_srli_epi32(v_fd_id_mask, 31);
> - v_fd_id_mask = _mm_slli_epi32(v_fd_id_mask, FDIR_ID_BIT_SHIFT);
> + v_fd_id_mask = _mm_slli_epi32(v_fd_id_mask, I40E_FDIR_ID_BIT_SHIFT);
>
> /* The returned value must be combined into each mbuf. This is already
> * being done for RSS and VLAN mbuf olflags, so return bits to OR in.
> @@ -205,10 +204,9 @@ descs_to_fdir_16b(__m128i fltstat, __m128i descs[4], struct rte_mbuf **rx_pkt)
> descs[0] = _mm_blendv_epi8(descs[0], _mm_setzero_si128(), v_desc0_mask);
>
> /* Shift to 1 or 0 bit per u32 lane, then to RTE_MBUF_F_RX_FDIR_ID offset */
> - const uint32_t FDIR_ID_BIT_SHIFT = 13;
> - RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << FDIR_ID_BIT_SHIFT));
> + RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << I40E_FDIR_ID_BIT_SHIFT));
> __m128i v_mask_one_bit = _mm_srli_epi32(v_fdir_id_mask, 31);
> - return _mm_slli_epi32(v_mask_one_bit, FDIR_ID_BIT_SHIFT);
> + return _mm_slli_epi32(v_mask_one_bit, I40E_FDIR_ID_BIT_SHIFT);
> }
> #endif
>
> --
Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
> 2.43.0
@@ -278,6 +278,7 @@ enum i40e_flxpld_layer_idx {
#define I40E_DEFAULT_DCB_APP_PRIO 3
#define I40E_FDIR_PRG_PKT_CNT 128
+#define I40E_FDIR_ID_BIT_SHIFT 13
/*
* Struct to store flow created.
@@ -143,10 +143,9 @@ descs_to_fdir_32b(volatile union i40e_rx_desc *rxdp, struct rte_mbuf **rx_pkt)
/* convert fdir_id_mask into a single bit, then shift as required for
* correct location in the mbuf->olflags
*/
- const uint32_t FDIR_ID_BIT_SHIFT = 13;
- RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << FDIR_ID_BIT_SHIFT));
+ RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << I40E_FDIR_ID_BIT_SHIFT));
v_fd_id_mask = _mm_srli_epi32(v_fd_id_mask, 31);
- v_fd_id_mask = _mm_slli_epi32(v_fd_id_mask, FDIR_ID_BIT_SHIFT);
+ v_fd_id_mask = _mm_slli_epi32(v_fd_id_mask, I40E_FDIR_ID_BIT_SHIFT);
/* The returned value must be combined into each mbuf. This is already
* being done for RSS and VLAN mbuf olflags, so return bits to OR in.
@@ -205,10 +204,9 @@ descs_to_fdir_16b(__m128i fltstat, __m128i descs[4], struct rte_mbuf **rx_pkt)
descs[0] = _mm_blendv_epi8(descs[0], _mm_setzero_si128(), v_desc0_mask);
/* Shift to 1 or 0 bit per u32 lane, then to RTE_MBUF_F_RX_FDIR_ID offset */
- const uint32_t FDIR_ID_BIT_SHIFT = 13;
- RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << FDIR_ID_BIT_SHIFT));
+ RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << I40E_FDIR_ID_BIT_SHIFT));
__m128i v_mask_one_bit = _mm_srli_epi32(v_fdir_id_mask, 31);
- return _mm_slli_epi32(v_mask_one_bit, FDIR_ID_BIT_SHIFT);
+ return _mm_slli_epi32(v_mask_one_bit, I40E_FDIR_ID_BIT_SHIFT);
}
#endif