[v3] net/i40e: workaround for Fortville performance
diff mbox series

Message ID 1528869161-94542-1-git-send-email-haiyue.wang@intel.com
State Accepted, archived
Delegated to: Qi Zhang
Headers show
Series
  • [v3] net/i40e: workaround for Fortville performance
Related show

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Haiyue Wang June 13, 2018, 5:52 a.m. UTC
The GL_SWR_PM_UP_THR value is not impacted from the link speed, its
value is set according to the total number of ports for a better
pipe-monitor configuration.

All bellowing relevant device IDs are considered (NICs, LOMs, Mezz
and Backplane):

Device-ID  Value        Comments
0x1572     0x03030303   10G SFI
0x1581     0x03030303   10G Backplane
0x1586     0x03030303   10G BaseT
0x1589     0x03030303   10G BaseT (FortPond)
0x1580     0x06060606   40G Backplane
0x1583     0x06060606   2x40G QSFP
0x1584     0x06060606   1x40G QSFP
0x1587     0x06060606   20G Backplane (HP)
0x1588     0x06060606   20G KR2 (HP)
0x158A     0x06060606   25G Backplane
0x158B     0x06060606   25G SFP28

Fixes: c9223a2bf53c ("i40e: workaround for XL710 performance")
Fixes: 75d133dd3296 ("net/i40e: enable 25G device")
Cc: stable@dpdk.org

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
---
v2 -> v3:
  - Change the return type of i40e_get_swr_pm_cfg from int to bool.

v1 -> v2:
  - The GL_SWR_PM_UP_THR register size is 4B, so change the table
    value type from uint64_t to uint32_t to reduce the table size.
  - Fix two CAMELCASE coding style errors.
---
 drivers/net/i40e/i40e_ethdev.c | 71 +++++++++++++++++++++++++++++++++++++-----
 1 file changed, 64 insertions(+), 7 deletions(-)

Comments

Zhang, Qi Z June 15, 2018, 2:07 p.m. UTC | #1
> -----Original Message-----
> From: Wang, Haiyue
> Sent: Wednesday, June 13, 2018 1:53 PM
> To: dev@dpdk.org
> Cc: Wang, Haiyue <haiyue.wang@intel.com>; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>; Yang, Qiming
> <qiming.yang@intel.com>; stable@dpdk.org
> Subject: [PATCH v3] net/i40e: workaround for Fortville performance
> 
> The GL_SWR_PM_UP_THR value is not impacted from the link speed, its
> value is set according to the total number of ports for a better pipe-monitor
> configuration.
> 
> All bellowing relevant device IDs are considered (NICs, LOMs, Mezz and
> Backplane):
> 
> Device-ID  Value        Comments
> 0x1572     0x03030303   10G SFI
> 0x1581     0x03030303   10G Backplane
> 0x1586     0x03030303   10G BaseT
> 0x1589     0x03030303   10G BaseT (FortPond)
> 0x1580     0x06060606   40G Backplane
> 0x1583     0x06060606   2x40G QSFP
> 0x1584     0x06060606   1x40G QSFP
> 0x1587     0x06060606   20G Backplane (HP)
> 0x1588     0x06060606   20G KR2 (HP)
> 0x158A     0x06060606   25G Backplane
> 0x158B     0x06060606   25G SFP28
> 
> Fixes: c9223a2bf53c ("i40e: workaround for XL710 performance")
> Fixes: 75d133dd3296 ("net/i40e: enable 25G device")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>

Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Zhang, Qi Z June 21, 2018, 2:35 p.m. UTC | #2
> -----Original Message-----
> From: Zhang, Qi Z
> Sent: Friday, June 15, 2018 10:07 PM
> To: Wang, Haiyue <haiyue.wang@intel.com>; dev@dpdk.org
> Cc: Wu, Jingjing <jingjing.wu@intel.com>; Yang, Qiming
> <qiming.yang@intel.com>; stable@dpdk.org
> Subject: RE: [PATCH v3] net/i40e: workaround for Fortville performance
> 
> 
> 
> > -----Original Message-----
> > From: Wang, Haiyue
> > Sent: Wednesday, June 13, 2018 1:53 PM
> > To: dev@dpdk.org
> > Cc: Wang, Haiyue <haiyue.wang@intel.com>; Zhang, Qi Z
> > <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>; Yang,
> > Qiming <qiming.yang@intel.com>; stable@dpdk.org
> > Subject: [PATCH v3] net/i40e: workaround for Fortville performance
> >
> > The GL_SWR_PM_UP_THR value is not impacted from the link speed, its
> > value is set according to the total number of ports for a better
> > pipe-monitor configuration.
> >
> > All bellowing relevant device IDs are considered (NICs, LOMs, Mezz and
> > Backplane):
> >
> > Device-ID  Value        Comments
> > 0x1572     0x03030303   10G SFI
> > 0x1581     0x03030303   10G Backplane
> > 0x1586     0x03030303   10G BaseT
> > 0x1589     0x03030303   10G BaseT (FortPond)
> > 0x1580     0x06060606   40G Backplane
> > 0x1583     0x06060606   2x40G QSFP
> > 0x1584     0x06060606   1x40G QSFP
> > 0x1587     0x06060606   20G Backplane (HP)
> > 0x1588     0x06060606   20G KR2 (HP)
> > 0x158A     0x06060606   25G Backplane
> > 0x158B     0x06060606   25G SFP28
> >
> > Fixes: c9223a2bf53c ("i40e: workaround for XL710 performance")
> > Fixes: 75d133dd3296 ("net/i40e: enable 25G device")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
> 
> Acked-by: Qi Zhang <qi.z.zhang@intel.com>

Applied to dpdk-next-net-intel

Thanks!
Qi

Patch
diff mbox series

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 13c5d32..ef17de8 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -10003,6 +10003,60 @@  i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
 
+/*
+ * GL_SWR_PM_UP_THR:
+ * The value is not impacted from the link speed, its value is set according
+ * to the total number of ports for a better pipe-monitor configuration.
+ */
+static bool
+i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
+{
+#define I40E_GL_SWR_PM_EF_DEVICE(dev) \
+		.device_id = (dev),   \
+		.val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
+
+#define I40E_GL_SWR_PM_SF_DEVICE(dev) \
+		.device_id = (dev),   \
+		.val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
+
+	static const struct {
+		uint16_t device_id;
+		uint32_t val;
+	} swr_pm_table[] = {
+		{ I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
+		{ I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
+		{ I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
+		{ I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
+
+		{ I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
+		{ I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
+		{ I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
+		{ I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
+		{ I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
+		{ I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
+		{ I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
+	};
+	uint32_t i;
+
+	if (value == NULL) {
+		PMD_DRV_LOG(ERR, "value is NULL");
+		return false;
+	}
+
+	for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
+		if (hw->device_id == swr_pm_table[i].device_id) {
+			*value = swr_pm_table[i].val;
+
+			PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
+				    "value - 0x%08x",
+				    hw->device_id, *value);
+			return true;
+		}
+	}
+
+	return false;
+}
+
 static int
 i40e_dev_sync_phy_type(struct i40e_hw *hw)
 {
@@ -10067,13 +10121,16 @@  i40e_configure_registers(struct i40e_hw *hw)
 		}
 
 		if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
-			if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
-			    I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
-				reg_table[i].val =
-					I40E_GL_SWR_PM_UP_THR_SF_VALUE;
-			else /* For X710 */
-				reg_table[i].val =
-					I40E_GL_SWR_PM_UP_THR_EF_VALUE;
+			uint32_t cfg_val;
+
+			if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
+				PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
+					    "GL_SWR_PM_UP_THR value fixup",
+					    hw->device_id);
+				continue;
+			}
+
+			reg_table[i].val = cfg_val;
 		}
 
 		ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,