diff mbox series

[08/11] net/sfc/base: guard Rx scale code with corresponding option

Message ID 1537797030-26548-9-git-send-email-arybchenko@solarflare.com (mailing list archive)
State Accepted, archived
Delegated to: Ferruh Yigit
Headers
Series net/sfc: update base driver to support 50G and 100G |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Andrew Rybchenko Sept. 24, 2018, 1:50 p.m. UTC 
  From: Tom Millington <tmillington@solarflare.com>

Previously only some of the code was guarded by this which caused
a build error when EFSYS_OPT_RX_SCALE is 0 (e.g. in manftest).

Signed-off-by: Tom Millington <tmillington@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
 drivers/net/sfc/base/ef10_nic.c  | 7 +++++++
 drivers/net/sfc/base/efx.h       | 2 ++
 drivers/net/sfc/base/siena_nic.c | 2 ++
 3 files changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index c197ff957..1b3d60682 100644
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1086,11 +1086,13 @@  ef10_get_datapath_caps(
 	}
 	encp->enc_rx_prefix_size = 14;
 
+#if EFSYS_OPT_RX_SCALE
 	/* Check if the firmware supports additional RSS modes */
 	if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
 		encp->enc_rx_scale_additional_modes_supported = B_TRUE;
 	else
 		encp->enc_rx_scale_additional_modes_supported = B_FALSE;
+#endif /* EFSYS_OPT_RX_SCALE */
 
 	/* Check if the firmware supports TSO */
 	if (CAP_FLAGS1(req, TX_TSO))
@@ -1296,6 +1298,7 @@  ef10_get_datapath_caps(
 	else
 		encp->enc_hlb_counters = B_FALSE;
 
+#if EFSYS_OPT_RX_SCALE
 	if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
 		/* Only one exclusive RSS context is available per port. */
 		encp->enc_rx_scale_max_exclusive_contexts = 1;
@@ -1345,6 +1348,8 @@  ef10_get_datapath_caps(
 		 */
 		encp->enc_rx_scale_l4_hash_supported = B_TRUE;
 	}
+#endif /* EFSYS_OPT_RX_SCALE */
+
 	/* Check if the firmware supports "FLAG" and "MARK" filter actions */
 	if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
 		encp->enc_filter_action_flag_supported = B_TRUE;
@@ -1368,8 +1373,10 @@  ef10_get_datapath_caps(
 
 	return (0);
 
+#if EFSYS_OPT_RX_SCALE
 fail5:
 	EFSYS_PROBE(fail5);
+#endif /* EFSYS_OPT_RX_SCALE */
 fail4:
 	EFSYS_PROBE(fail4);
 fail3:
diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h
index a8c3ae301..246708f9c 100644
--- a/drivers/net/sfc/base/efx.h
+++ b/drivers/net/sfc/base/efx.h
@@ -1281,6 +1281,7 @@  typedef struct efx_nic_cfg_s {
 	uint32_t		enc_rx_prefix_size;
 	uint32_t		enc_rx_buf_align_start;
 	uint32_t		enc_rx_buf_align_end;
+#if EFSYS_OPT_RX_SCALE
 	uint32_t		enc_rx_scale_max_exclusive_contexts;
 	/*
 	 * Mask of supported hash algorithms.
@@ -1293,6 +1294,7 @@  typedef struct efx_nic_cfg_s {
 	 */
 	boolean_t		enc_rx_scale_l4_hash_supported;
 	boolean_t		enc_rx_scale_additional_modes_supported;
+#endif /* EFSYS_OPT_RX_SCALE */
 #if EFSYS_OPT_LOOPBACK
 	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
 #endif	/* EFSYS_OPT_LOOPBACK */
diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c
index 8a58986e8..fca17171b 100644
--- a/drivers/net/sfc/base/siena_nic.c
+++ b/drivers/net/sfc/base/siena_nic.c
@@ -114,6 +114,7 @@  siena_board_cfg(
 	/* Alignment for WPTR updates */
 	encp->enc_rx_push_align = 1;
 
+#if EFSYS_OPT_RX_SCALE
 	/* There is one RSS context per function */
 	encp->enc_rx_scale_max_exclusive_contexts = 1;
 
@@ -128,6 +129,7 @@  siena_board_cfg(
 
 	/* There is no support for additional RSS modes */
 	encp->enc_rx_scale_additional_modes_supported = B_FALSE;
+#endif /* EFSYS_OPT_RX_SCALE */
 
 	encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
 	/* Fragments must not span 4k boundaries. */