diff mbox series

[v4,2/5] meson: add infra to support machine specific flags

Message ID 20190109103915.29210-2-pbhagavatula@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series [v4,1/5] mk: introduce helper to check valid compiler argument |

Checks

Context Check Description
ci/Intel-compilation success Compilation OK

Commit Message

Pavan Nikhilesh Bhagavatula Jan. 9, 2019, 10:39 a.m. UTC 
  From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE.
Add support to set micro arch specific flags.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 config/arm/meson.build | 53 +++++++++++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 21 deletions(-)

Comments

Thomas Monjalon Jan. 14, 2019, 11:32 a.m. UTC | #1 
09/01/2019 11:39, Pavan Nikhilesh Bhagavatula:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE.
> Add support to set micro arch specific flags.
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
>  	['RTE_CACHE_LINE_SIZE', 128],
>  	['RTE_MAX_NUMA_NODES', 2],
>  	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
[...]
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
[..]
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]

This patch is not only adding infra, it also change some Cavium config.
What about splitting, and explaining the change of RTE_USE_C11_MEM_MODEL?
Phil Yang Feb. 12, 2019, 8:06 a.m. UTC | #2 
Hi Pavan,

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Pavan Nikhilesh Bhagavatula
> Sent: Wednesday, January 9, 2019 6:40 PM
> To: jerinj@marvell.com; Gavin Hu (Arm Technology China)
> <Gavin.Hu@arm.com>; bruce.richardson@intel.com; thomas@monjalon.net
> Cc: dev@dpdk.org; Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
> Subject: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific
> flags
> 
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might be
> some micro arch specific differences from the same vendor eg. CACHE_LINESIZE.
> Add support to set micro arch specific flags.
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> ---
>  config/arm/meson.build | 53 +++++++++++++++++++++++++-----------------
>  1 file changed, 32 insertions(+), 21 deletions(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> dae55d6b2..576363fc0 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -7,23 +7,6 @@ march_opt = '-march=@0@'.format(machine)
> 
>  arm_force_native_march = false
> 
> -machine_args_generic = [
> -	['default', ['-march=armv8-a+crc+crypto']],
> -	['native', ['-march=native']],
> -	['0xd03', ['-mcpu=cortex-a53']],
> -	['0xd04', ['-mcpu=cortex-a35']],
> -	['0xd07', ['-mcpu=cortex-a57']],
> -	['0xd08', ['-mcpu=cortex-a72']],
> -	['0xd09', ['-mcpu=cortex-a73']],
> -	['0xd0a', ['-mcpu=cortex-a75']],
> -]
> -machine_args_cavium = [
> -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> -	['native', ['-march=native']],
> -	['0xa1', ['-mcpu=thunderxt88']],
> -	['0xa2', ['-mcpu=thunderxt81']],
> -	['0xa3', ['-mcpu=thunderxt83']]]
> -
>  flags_common_default = [
>  	# Accelarate rte_memcpy. Be sure to run unit test
> (memcpy_perf_autotest)
>  	# to determine the best threshold in code. Refer to notes in source file
> @@ -50,12 +33,10 @@ flags_generic = [
>  	['RTE_USE_C11_MEM_MODEL', true],
>  	['RTE_CACHE_LINE_SIZE', 128]]
>  flags_cavium = [
> -	['RTE_MACHINE', '"thunderx"'],
>  	['RTE_CACHE_LINE_SIZE', 128],
>  	['RTE_MAX_NUMA_NODES', 2],
>  	['RTE_MAX_LCORE', 96],
> -	['RTE_MAX_VFIO_GROUPS', 128],
> -	['RTE_USE_C11_MEM_MODEL', false]]
> +	['RTE_MAX_VFIO_GROUPS', 128]]
>  flags_dpaa = [
>  	['RTE_MACHINE', '"dpaa"'],
>  	['RTE_USE_C11_MEM_MODEL', true],
> @@ -69,6 +50,27 @@ flags_dpaa2 = [
>  	['RTE_MAX_NUMA_NODES', 1],
>  	['RTE_MAX_LCORE', 16],
>  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> +flags_default_extra = []
> +flags_thunderx_extra = [
> +	['RTE_MACHINE', '"thunderx"'],
> +	['RTE_USE_C11_MEM_MODEL', false]]
> +
> +machine_args_generic = [
> +	['default', ['-march=armv8-a+crc+crypto']],
> +	['native', ['-march=native']],
> +	['0xd03', ['-mcpu=cortex-a53']],
> +	['0xd04', ['-mcpu=cortex-a35']],
> +	['0xd07', ['-mcpu=cortex-a57']],
> +	['0xd08', ['-mcpu=cortex-a72']],
> +	['0xd09', ['-mcpu=cortex-a73']],
> +	['0xd0a', ['-mcpu=cortex-a75']]]
> +
> +machine_args_cavium = [
> +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> +	['native', ['-march=native']],
> +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> 
>  ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
> impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -
> 157,10 +159,19 @@ else
>  	foreach marg: machine[2]
>  		if marg[0] == impl_pn
>  			foreach f: marg[1]
> -				machine_args += f
> +				if cc.has_argument(f)
> +					machine_args += f
> +				endif
>  			endforeach
>  		endif
>  	endforeach
> +
> +	# Apply any extra machine specific flags.
> +	foreach flag: marg.get(2, flags_default_extra)
> +		if flag.length() > 0
> +			dpdk_conf.set(flag[0], flag[1])
> +		endif
> +	endforeach

I think this loop should put inside the 'if marg[0] == impl_pn' condition.
The right logic should be:
If marg[0] == impl_pn
	# update machine_args
	# Apply any extra machine specific flags
endif

I tested this patch on thunderx2, but it set the octeontx2 extra flags into the rte_build_config.h. Because octeontx2 is the last item of 'machine_args_cavium' table.

>  endif
>  message(machine_args)
> 
> --
> 2.20.1

Thanks,
Phil Yang.
Pavan Nikhilesh Bhagavatula Feb. 12, 2019, 8:35 a.m. UTC | #3 
Hi Phil,

On Tue, 2019-02-12 at 08:06 +0000, Phil Yang (Arm Technology China)
wrote:
> External Email
> 
> -------------------------------------------------------------------
> ---
> Hi Pavan,
> 
> > -----Original Message-----
> > From: dev <dev-bounces@dpdk.org> On Behalf Of Pavan Nikhilesh
> > Bhagavatula
> > Sent: Wednesday, January 9, 2019 6:40 PM
> > To: jerinj@marvell.com; Gavin Hu (Arm Technology China)
> > <Gavin.Hu@arm.com>; bruce.richardson@intel.com; thomas@monjalon.net
> > Cc: dev@dpdk.org; Pavan Nikhilesh Bhagavatula <
> > pbhagavatula@marvell.com>
> > Subject: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support
> > machine specific
> > flags
> > 
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > 
> > Currently, RTE_* flags are set based on the implementer ID but
> > there might be
> > some micro arch specific differences from the same vendor eg.
> > CACHE_LINESIZE.
> > Add support to set micro arch specific flags.
> > 
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > ---
> >  config/arm/meson.build | 53 +++++++++++++++++++++++++-------------
> > ----
> >  1 file changed, 32 insertions(+), 21 deletions(-)
> > 
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > dae55d6b2..576363fc0 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -7,23 +7,6 @@ march_opt = '-march=@0@'.format(machine)
> > 
> >  arm_force_native_march = false
> > 
> > -machine_args_generic = [
> > -	['default', ['-march=armv8-a+crc+crypto']],
> > -	['native', ['-march=native']],
> > -	['0xd03', ['-mcpu=cortex-a53']],
> > -	['0xd04', ['-mcpu=cortex-a35']],
> > -	['0xd07', ['-mcpu=cortex-a57']],
> > -	['0xd08', ['-mcpu=cortex-a72']],
> > -	['0xd09', ['-mcpu=cortex-a73']],
> > -	['0xd0a', ['-mcpu=cortex-a75']],
> > -]
> > -machine_args_cavium = [
> > -	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > -	['native', ['-march=native']],
> > -	['0xa1', ['-mcpu=thunderxt88']],
> > -	['0xa2', ['-mcpu=thunderxt81']],
> > -	['0xa3', ['-mcpu=thunderxt83']]]
> > -
> >  flags_common_default = [
> >  	# Accelarate rte_memcpy. Be sure to run unit test
> > (memcpy_perf_autotest)
> >  	# to determine the best threshold in code. Refer to notes in
> > source file
> > @@ -50,12 +33,10 @@ flags_generic = [
> >  	['RTE_USE_C11_MEM_MODEL', true],
> >  	['RTE_CACHE_LINE_SIZE', 128]]
> >  flags_cavium = [
> > -	['RTE_MACHINE', '"thunderx"'],
> >  	['RTE_CACHE_LINE_SIZE', 128],
> >  	['RTE_MAX_NUMA_NODES', 2],
> >  	['RTE_MAX_LCORE', 96],
> > -	['RTE_MAX_VFIO_GROUPS', 128],
> > -	['RTE_USE_C11_MEM_MODEL', false]]
> > +	['RTE_MAX_VFIO_GROUPS', 128]]
> >  flags_dpaa = [
> >  	['RTE_MACHINE', '"dpaa"'],
> >  	['RTE_USE_C11_MEM_MODEL', true],
> > @@ -69,6 +50,27 @@ flags_dpaa2 = [
> >  	['RTE_MAX_NUMA_NODES', 1],
> >  	['RTE_MAX_LCORE', 16],
> >  	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
> > +flags_default_extra = []
> > +flags_thunderx_extra = [
> > +	['RTE_MACHINE', '"thunderx"'],
> > +	['RTE_USE_C11_MEM_MODEL', false]]
> > +
> > +machine_args_generic = [
> > +	['default', ['-march=armv8-a+crc+crypto']],
> > +	['native', ['-march=native']],
> > +	['0xd03', ['-mcpu=cortex-a53']],
> > +	['0xd04', ['-mcpu=cortex-a35']],
> > +	['0xd07', ['-mcpu=cortex-a57']],
> > +	['0xd08', ['-mcpu=cortex-a72']],
> > +	['0xd09', ['-mcpu=cortex-a73']],
> > +	['0xd0a', ['-mcpu=cortex-a75']]]
> > +
> > +machine_args_cavium = [
> > +	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > +	['native', ['-march=native']],
> > +	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
> > +	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
> > +	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
> > 
> >  ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-
> > 5321)
> > impl_generic = ['Generic armv8', flags_generic,
> > machine_args_generic] @@ -
> > 157,10 +159,19 @@ else
> >  	foreach marg: machine[2]
> >  		if marg[0] == impl_pn
> >  			foreach f: marg[1]
> > -				machine_args += f
> > +				if cc.has_argument(f)
> > +					machine_args += f
> > +				endif
> >  			endforeach
> >  		endif
> >  	endforeach
> > +
> > +	# Apply any extra machine specific flags.
> > +	foreach flag: marg.get(2, flags_default_extra)
> > +		if flag.length() > 0
> > +			dpdk_conf.set(flag[0], flag[1])
> > +		endif
> > +	endforeach
> 
> I think this loop should put inside the 'if marg[0] == impl_pn'
> condition.
> The right logic should be:
> If marg[0] == impl_pn
> 	# update machine_args
> 	# Apply any extra machine specific flags
> endif

Yes, you are correct I will modify this in the next version.

Thanks,
Pavan.
> 
> I tested this patch on thunderx2, but it set the octeontx2 extra
> flags into the rte_build_config.h. Because octeontx2 is the last item
> of 'machine_args_cavium' table.
> 
> >  endif
> >  message(machine_args)
> > 
> > --
> > 2.20.1
> 
> Thanks,
> Phil Yang.
diff mbox series

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index dae55d6b2..576363fc0 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -7,23 +7,6 @@  march_opt = '-march=@0@'.format(machine)
 
 arm_force_native_march = false
 
-machine_args_generic = [
-	['default', ['-march=armv8-a+crc+crypto']],
-	['native', ['-march=native']],
-	['0xd03', ['-mcpu=cortex-a53']],
-	['0xd04', ['-mcpu=cortex-a35']],
-	['0xd07', ['-mcpu=cortex-a57']],
-	['0xd08', ['-mcpu=cortex-a72']],
-	['0xd09', ['-mcpu=cortex-a73']],
-	['0xd0a', ['-mcpu=cortex-a75']],
-]
-machine_args_cavium = [
-	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
-	['native', ['-march=native']],
-	['0xa1', ['-mcpu=thunderxt88']],
-	['0xa2', ['-mcpu=thunderxt81']],
-	['0xa3', ['-mcpu=thunderxt83']]]
-
 flags_common_default = [
 	# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 	# to determine the best threshold in code. Refer to notes in source file
@@ -50,12 +33,10 @@  flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -69,6 +50,27 @@  flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,10 +159,19 @@  else
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
 			foreach f: marg[1]
-				machine_args += f
+				if cc.has_argument(f)
+					machine_args += f
+				endif
 			endforeach
 		endif
 	endforeach
+
+	# Apply any extra machine specific flags.
+	foreach flag: marg.get(2, flags_default_extra)
+		if flag.length() > 0
+			dpdk_conf.set(flag[0], flag[1])
+		endif
+	endforeach
 endif
 message(machine_args)