From patchwork Mon Mar 11 07:04:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 51056 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 22BFD1B137; Mon, 11 Mar 2019 08:03:40 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 5D33C1B12B for ; Mon, 11 Mar 2019 08:03:38 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Mar 2019 00:03:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,467,1544515200"; d="scan'208";a="124386219" Received: from dpdk51.sh.intel.com ([10.67.110.160]) by orsmga008.jf.intel.com with ESMTP; 11 Mar 2019 00:03:36 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, paul.m.stillwell.jr@intel.com, ferruh.yigit@intel.com, Qi Zhang Date: Mon, 11 Mar 2019 15:04:28 +0800 Message-Id: <20190311070441.5501-26-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190311070441.5501-1-qi.z.zhang@intel.com> References: <20190228055650.25237-1-qi.z.zhang@intel.com> <20190311070441.5501-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 25/38] net/ice/base: minor fix X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 1. Fix some problems with filling the HW tables. 2. Fix a logic error in ice_rem_prof_from_list. Fixes: 51d04e4933e3 ("net/ice/base: add flexible pipeline module") Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flex_pipe.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 887609204..1dd121b28 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -2935,9 +2935,11 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid) while (sect) { switch (sid) { + case ICE_SID_XLT1_SW: case ICE_SID_XLT1_FD: case ICE_SID_XLT1_RSS: case ICE_SID_XLT1_ACL: + case ICE_SID_XLT1_PE: xlt1 = (struct ice_xlt1_section *)sect; src = xlt1->value; sect_len = LE16_TO_CPU(xlt1->count) * @@ -2946,9 +2948,11 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid) dst_len = hw->blk[block_id].xlt1.count * sizeof(*hw->blk[block_id].xlt1.t); break; + case ICE_SID_XLT2_SW: case ICE_SID_XLT2_FD: case ICE_SID_XLT2_RSS: case ICE_SID_XLT2_ACL: + case ICE_SID_XLT2_PE: xlt2 = (struct ice_xlt2_section *)sect; src = (u8 *)xlt2->value; sect_len = LE16_TO_CPU(xlt2->count) * @@ -2957,9 +2961,11 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid) dst_len = hw->blk[block_id].xlt2.count * sizeof(*hw->blk[block_id].xlt2.t); break; + case ICE_SID_PROFID_TCAM_SW: case ICE_SID_PROFID_TCAM_FD: case ICE_SID_PROFID_TCAM_RSS: case ICE_SID_PROFID_TCAM_ACL: + case ICE_SID_PROFID_TCAM_PE: pid = (struct ice_prof_id_section *)sect; src = (u8 *)pid->entry; sect_len = LE16_TO_CPU(pid->count) * @@ -2968,9 +2974,11 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid) dst_len = hw->blk[block_id].prof.count * sizeof(*hw->blk[block_id].prof.t); break; + case ICE_SID_PROFID_REDIR_SW: case ICE_SID_PROFID_REDIR_FD: case ICE_SID_PROFID_REDIR_RSS: case ICE_SID_PROFID_REDIR_ACL: + case ICE_SID_PROFID_REDIR_PE: pr = (struct ice_prof_redir_section *)sect; src = pr->redir_value; sect_len = LE16_TO_CPU(pr->count) * @@ -2979,15 +2987,19 @@ static void ice_fill_tbl(struct ice_hw *hw, enum ice_block block_id, u32 sid) dst_len = hw->blk[block_id].prof_redir.count * sizeof(*hw->blk[block_id].prof_redir.t); break; + case ICE_SID_FLD_VEC_SW: case ICE_SID_FLD_VEC_FD: case ICE_SID_FLD_VEC_RSS: case ICE_SID_FLD_VEC_ACL: + case ICE_SID_FLD_VEC_PE: es = (struct ice_sw_fv_section *)sect; src = (u8 *)es->fv; sect_len = LE16_TO_CPU(es->count) * - sizeof(*hw->blk[block_id].prof_redir.t); + hw->blk[block_id].es.fvw * + sizeof(*hw->blk[block_id].es.t); dst = (u8 *)hw->blk[block_id].es.t; dst_len = hw->blk[block_id].es.count * + hw->blk[block_id].es.fvw * sizeof(*hw->blk[block_id].es.t); break; default: @@ -4964,8 +4976,8 @@ ice_rem_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl) if (status) goto err_ice_rem_prof_id_flow; - } else if (ice_find_dup_props_vsig(hw, blk, ©, - &vsig)) { + } else if (!ice_find_dup_props_vsig(hw, blk, ©, + &vsig)) { /* found an exact match */ /* add or move VSI to the VSIG that matches */ /* Search for a VSIG with a matching profile