From patchwork Thu Apr 4 20:54:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduard Serra X-Patchwork-Id: 52312 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 602911B3A7; Thu, 4 Apr 2019 22:54:23 +0200 (CEST) Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by dpdk.org (Postfix) with ESMTP id 4A7111B394 for ; Thu, 4 Apr 2019 22:54:22 +0200 (CEST) Received: by mail-pg1-f194.google.com with SMTP id p6so1809898pgh.9 for ; Thu, 04 Apr 2019 13:54:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=TtIeDOURtmGdoFugNhKpVGg/M+gSJQSla1UVzJAJqJM=; b=QSB8QAGUsjegJVYnng/ahPBytci+/8QYRbkszKy9zdoiyOR7Tcmq748O21tOuFshJS KHJjkIpX5m0uI6CbG++jO8csLTu4XJaCN/hxEUmBLV9TOIP4nbWH3NcxUH7Hd4M8moLZ 6IAWnGmYH7ukF+G36CXVe2S1TNf+gnbKaknFAaOkLLJeFfUZqTytXzfspTydGwVvDoQa SN/e+m/3Z0I62iq5c1+IXSfP+z/H0O/jny16wEGkeFxQhuq9D9IcB86WK5cRp/SmwOUA haDMx445pp8T7diJs/exLORl1KzV/riwYSt0KlT8EbPPjVKu7IRpp7aOsN2Rn6Xu0uAz ZlRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=TtIeDOURtmGdoFugNhKpVGg/M+gSJQSla1UVzJAJqJM=; b=P8PIOC/leUygfIhtEcVfDVgmCMdmSX5s9pjuEwInE1N91Uy9SQGO+nYDbDUtiqm89q fNWhfY97ErEVSVEuA1MGaS3tkXuKp2UaC/cXzhgGRqcADpQEQ3Sk5N5mV5nIWIZ8VEeh kn2NO4d1mH/rzV14NjGjVz0AX2bhnMOb8UJgvuCN82Es4zhEjW5/x0yTsgdSkqQshLrc UVZGOsfnQZIPZklc2hdIVQXFP0YzoscV9slArP+f14U3CnKmITzh50LPG2LelpspbIyp CRFfCXB7sdzruLoL2N3SJXuZMZE6H2xwjv9UogN0bD59uLDiSvICGdHQ5GJiOYtT7eP6 SZpQ== X-Gm-Message-State: APjAAAV+nSV3On6CDCJQusE7R90G39oE+jqV9xUejB4K71F0wE14/nRv ClIqZQi3HhF/cOXsJyM0MiR75UaFYU0= X-Google-Smtp-Source: APXvYqwL22sMZck+ZRu/nLfazD+dkEJ6hU8jQkxCResxNHgoJAUiGFIJhXZ1TRsO14LMQyZ64yTN4g== X-Received: by 2002:a65:5c42:: with SMTP id v2mr7768957pgr.360.1554411261206; Thu, 04 Apr 2019 13:54:21 -0700 (PDT) Received: from dev.localdomain ([66.170.99.2]) by smtp.gmail.com with ESMTPSA id n3sm34297277pfa.99.2019.04.04.13.54.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Apr 2019 13:54:20 -0700 (PDT) From: eduser25@gmail.com X-Google-Original-From: eserra@vmware.com To: yongwang@vmware.com Cc: dev@dpdk.org, Eduard Serra Date: Thu, 4 Apr 2019 13:54:11 -0700 Message-Id: <1554411251-67227-1-git-send-email-eserra@vmware.com> X-Mailer: git-send-email 2.7.4 Subject: [dpdk-dev] [PATCH] net/vmxnet3: synchronize vmxnet definitions with 6.7 public X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Eduard Serra Synchronize new definitions made public defs on ESX 6.7, which include support for variety of new features and fixes on vmxnet3 driver. Signed-off-by: Eduard Serra --- drivers/net/vmxnet3/base/vmxnet3_defs.h | 296 ++++++++++++++++++++++++++------ 1 file changed, 245 insertions(+), 51 deletions(-) diff --git a/drivers/net/vmxnet3/base/vmxnet3_defs.h b/drivers/net/vmxnet3/base/vmxnet3_defs.h index bbec708..3f2a80d 100644 --- a/drivers/net/vmxnet3/base/vmxnet3_defs.h +++ b/drivers/net/vmxnet3/base/vmxnet3_defs.h @@ -86,9 +86,11 @@ typedef enum { VMXNET3_CMD_STOP_EMULATION, VMXNET3_CMD_LOAD_PLUGIN, VMXNET3_CMD_ACTIVATE_VF, - VMXNET3_CMD_RESERVED3, - VMXNET3_CMD_RESERVED4, + VMXNET3_CMD_SET_POLLING, + VMXNET3_CMD_SET_COALESCE, VMXNET3_CMD_REGISTER_MEMREGS, + VMXNET3_CMD_SET_RSS_FIELDS, + VMXNET3_CMD_SET_PKTSTEERING, VMXNET3_CMD_FIRST_GET = 0xF00D0000, VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, @@ -102,7 +104,10 @@ typedef enum { VMXNET3_CMD_GET_CONF_INTR, VMXNET3_CMD_GET_ADAPTIVE_RING_INFO, VMXNET3_CMD_GET_TXDATA_DESC_SIZE, - VMXNET3_CMD_RESERVED5, + VMXNET3_CMD_GET_COALESCE, + VMXNET3_CMD_GET_RSS_FIELDS, + VMXNET3_CMD_GET_ENCAP_DSTPORT, + VMXNET3_CMD_GET_PKTSTEERING, } Vmxnet3_Cmd; /* Adaptive Ring Info Flags */ @@ -111,14 +116,14 @@ typedef enum { /* * Little Endian layout of bitfields - * Byte 0 : 7.....len.....0 - * Byte 1 : rsvd gen 13.len.8 - * Byte 2 : 5.msscof.0 ext1 dtype - * Byte 3 : 13...msscof...6 + * Byte 1 : oco gen 13.len.8 + * Byte 2 : 5.msscof.0 ext1 dtype + * Byte 3 : 13...msscof...6 * * Big Endian layout of bitfields - * Byte 0: 13...msscof...6 - * Byte 1 : 5.msscof.0 ext1 dtype - * Byte 2 : rsvd gen 13.len.8 + * Byte 1 : 5.msscof.0 ext1 dtype + * Byte 2 : oco gen 13.len.8 * Byte 3 : 7.....len.....0 * * Thus, le32_to_cpu on the dword will allow the big endian driver to read @@ -135,13 +140,13 @@ struct Vmxnet3_TxDesc { uint32 msscof:14; /* MSS, checksum offset, flags */ uint32 ext1:1; uint32 dtype:1; /* descriptor type */ - uint32 rsvd:1; + uint32 oco:1; /* Outer csum offload */ uint32 gen:1; /* generation bit */ uint32 len:14; #else uint32 len:14; uint32 gen:1; /* generation bit */ - uint32 rsvd:1; + uint32 oco:1; /* Outer csum offload */ uint32 dtype:1; /* descriptor type */ uint32 ext1:1; uint32 msscof:14; /* MSS, checksum offset, flags */ @@ -169,9 +174,10 @@ struct Vmxnet3_TxDesc { Vmxnet3_TxDesc; /* TxDesc.OM values */ -#define VMXNET3_OM_NONE 0 -#define VMXNET3_OM_CSUM 2 -#define VMXNET3_OM_TSO 3 +#define VMXNET3_OM_NONE 0 /* 0b00 */ +#define VMXNET3_OM_ENCAP 1 /* 0b01 */ +#define VMXNET3_OM_CSUM 2 /* 0b10 */ +#define VMXNET3_OM_TSO 3 /* 0b11 */ /* fields in TxDesc we access w/o using bit fields */ #define VMXNET3_TXD_EOP_SHIFT 12 @@ -188,7 +194,6 @@ Vmxnet3_TxDesc; #define VMXNET3_TXD_EOP_SIZE 1 #define VMXNET3_HDR_COPY_SIZE 128 - typedef #include "vmware_pack_begin.h" struct Vmxnet3_TxDataDesc { @@ -196,6 +201,7 @@ struct Vmxnet3_TxDataDesc { } #include "vmware_pack_end.h" Vmxnet3_TxDataDesc; +typedef uint8 Vmxnet3_RxDataDesc; #define VMXNET3_TCD_GEN_SHIFT 31 #define VMXNET3_TCD_GEN_SIZE 1 @@ -324,31 +330,38 @@ struct Vmxnet3_RxCompDescExt { uint8 segCnt; /* Number of aggregated packets */ uint8 dupAckCnt; /* Number of duplicate Acks */ __le16 tsDelta; /* TCP timestamp difference */ - __le32 dword2; #ifdef __BIG_ENDIAN_BITFIELD - uint32 gen : 1; /* generation bit */ - uint32 type : 7; /* completion type */ - uint32 fcs : 1; /* Frame CRC correct */ - uint32 frg : 1; /* IP Fragment */ - uint32 v4 : 1; /* IPv4 */ - uint32 v6 : 1; /* IPv6 */ - uint32 ipc : 1; /* IP Checksum Correct */ - uint32 tcp : 1; /* TCP packet */ - uint32 udp : 1; /* UDP packet */ - uint32 tuc : 1; /* TCP/UDP Checksum Correct */ - uint32 mss : 16; + uint32 encap:1; /* LRO info refers to inner pkt */ + uint32 reserved:31; +#else + uint32 reserved:31; + uint32 encap:1; /* LRO info refers to inner pkt */ +#endif /* __BIG_ENDIAN_BITFIELD */ + +#ifdef __BIG_ENDIAN_BITFIELD + uint32 gen:1; /* generation bit */ + uint32 type:7; /* completion type */ + uint32 fcs:1; /* Frame CRC correct */ + uint32 frg:1; /* IP Fragment */ + uint32 v4:1; /* IPv4 */ + uint32 v6:1; /* IPv6 */ + uint32 ipc:1; /* IP Checksum Correct */ + uint32 tcp:1; /* TCP packet */ + uint32 udp:1; /* UDP packet */ + uint32 tuc:1; /* TCP/UDP Checksum Correct */ + uint32 mss:16; #else - uint32 mss : 16; - uint32 tuc : 1; /* TCP/UDP Checksum Correct */ - uint32 udp : 1; /* UDP packet */ - uint32 tcp : 1; /* TCP packet */ - uint32 ipc : 1; /* IP Checksum Correct */ - uint32 v6 : 1; /* IPv6 */ - uint32 v4 : 1; /* IPv4 */ - uint32 frg : 1; /* IP Fragment */ - uint32 fcs : 1; /* Frame CRC correct */ - uint32 type : 7; /* completion type */ - uint32 gen : 1; /* generation bit */ + uint32 mss:16; + uint32 tuc:1; /* TCP/UDP Checksum Correct */ + uint32 udp:1; /* UDP packet */ + uint32 tcp:1; /* TCP packet */ + uint32 ipc:1; /* IP Checksum Correct */ + uint32 v6:1; /* IPv6 */ + uint32 v4:1; /* IPv4 */ + uint32 frg:1; /* IP Fragment */ + uint32 fcs:1; /* Frame CRC correct */ + uint32 type:7; /* completion type */ + uint32 gen:1; /* generation bit */ #endif /* __BIG_ENDIAN_BITFIELD */ } #include "vmware_pack_end.h" @@ -371,6 +384,10 @@ Vmxnet3_RxCompDescExt; #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2 #define VMXNET3_RCD_RSS_TYPE_IPV6 3 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4 +#define VMXNET3_RCD_RSS_TYPE_UDPIPV4 5 +#define VMXNET3_RCD_RSS_TYPE_UDPIPV6 6 +#define VMXNET3_RCD_RSS_TYPE_ESPIPV4 7 +#define VMXNET3_RCD_RSS_TYPE_ESPIPV6 8 /* a union for accessing all cmd/completion descriptors */ typedef union Vmxnet3_GenericDesc { @@ -386,6 +403,8 @@ typedef union Vmxnet3_GenericDesc { #define VMXNET3_INIT_GEN 1 +#define VMXNET3_INVALID_QUEUEID -1 + /* Max size of a single tx buffer */ #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) @@ -409,24 +428,25 @@ typedef union Vmxnet3_GenericDesc { #define VMXNET3_RING_SIZE_ALIGN 32 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) -/* Tx Data Ring buffer size must be a multiple of 64 */ -#define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64 -#define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1) - -/* Rx Data Ring buffer size must be a multiple of 64 */ +/* Rx Data Ring buffer size must be a multiple of 64 bytes */ #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1) +/* Tx Data Ring buffer size must be a multiple of 64 bytes */ +#define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64 +#define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1) + /* Max ring size */ #define VMXNET3_TX_RING_MAX_SIZE 4096 #define VMXNET3_TC_RING_MAX_SIZE 4096 #define VMXNET3_RX_RING_MAX_SIZE 4096 +#define VMXNET3_RX_RING2_MAX_SIZE 4096 #define VMXNET3_RC_RING_MAX_SIZE 8192 -#define VMXNET3_TXDATA_DESC_MIN_SIZE 128 -#define VMXNET3_TXDATA_DESC_MAX_SIZE 2048 - -#define VMXNET3_RXDATA_DESC_MAX_SIZE 2048 +/* Large enough to accommodate typical payload + encap + extension header */ +#define VMXNET3_RXDATA_DESC_MAX_SIZE 2048 +#define VMXNET3_TXDATA_DESC_MIN_SIZE 128 +#define VMXNET3_TXDATA_DESC_MAX_SIZE 2048 /* a list of reasons for queue stop */ @@ -527,7 +547,7 @@ struct Vmxnet3_TxQueueConf { __le32 compRingSize; /* # of comp desc */ __le32 ddLen; /* size of driver data */ uint8 intrIdx; - uint8 _pad[1]; + uint8 _pad1[1]; __le16 txDataRingDescSize; uint8 _pad2[4]; } @@ -546,7 +566,7 @@ struct Vmxnet3_RxQueueConf { __le32 ddLen; /* size of driver data */ uint8 intrIdx; uint8 _pad1[1]; - __le16 rxDataRingDescSize; /* size of rx data ring buffer */ + __le16 rxDataRingDescSize; /* size of rx data ring buffer */ uint8 _pad2[4]; } #include "vmware_pack_end.h" @@ -573,6 +593,47 @@ enum vmxnet3_intr_type { /* value of intrCtrl */ #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ +#define VMXNET3_COAL_STATIC_MAX_DEPTH 128 +#define VMXNET3_COAL_RBC_MIN_RATE 100 +#define VMXNET3_COAL_RBC_MAX_RATE 100000 + +enum Vmxnet3_CoalesceMode { + VMXNET3_COALESCE_DISABLED = 0, + VMXNET3_COALESCE_ADAPT = 1, + VMXNET3_COALESCE_STATIC = 2, + VMXNET3_COALESCE_RBC = 3 +}; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_CoalesceRbc { + uint32 rbc_rate; +} +#include "vmware_pack_end.h" +Vmxnet3_CoalesceRbc; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_CoalesceStatic { + uint32 tx_depth; + uint32 tx_comp_depth; + uint32 rx_depth; +} +#include "vmware_pack_end.h" +Vmxnet3_CoalesceStatic; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_CoalesceScheme { + enum Vmxnet3_CoalesceMode coalMode; + union { + Vmxnet3_CoalesceRbc coalRbc; + Vmxnet3_CoalesceStatic coalStatic; + } coalPara; +} +#include "vmware_pack_end.h" +Vmxnet3_CoalesceScheme; + typedef #include "vmware_pack_begin.h" struct Vmxnet3_IntrConf { @@ -637,6 +698,110 @@ struct Vmxnet3_RxFilterConf { #include "vmware_pack_end.h" Vmxnet3_RxFilterConf; +#define ETH_ADDR_LENGTH 6 + +#define VMXNET3_PKTSTEERING_VERSION_ONE 1 +#define VMXNET3_PKTSTEERING_CURRENT_VERSION VMXNET3_PKTSTEERING_VERSION_ONE + +typedef uint8_t Eth_Address[ETH_ADDR_LENGTH]; + + +typedef enum { + VMXNET3_PKTSTEERING_NOACTION, + VMXNET3_PKTSTEERING_ACCEPT, + VMXNET3_PKTSTEERING_REJECT, + VMXNET3_PKTSTEERING_ACTION_MAX, +} Vmxnet3_PktSteeringAction; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_PktSteeringActionData { + uint8_t action; /* enum Vmxnet3PktSteeringAction */ + uint8_t rxQid; +} +#include "vmware_pack_end.h" +Vmxnet3_PktSteeringActionData; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_PktSteeringInput { + uint16_t l3proto; + uint8_t l4proto; + uint8_t pad; + + uint16_t srcPort; + uint16_t dstPort; + + union { + struct { + uint32_t srcIPv4; + uint32_t dstIPv4; + }; + struct { + uint8_t srcIPv6[16]; + uint8_t dstIPv6[16]; + }; + }; + + Eth_Address dstMAC; + Eth_Address srcMAC; +} +#include "vmware_pack_end.h" +Vmxnet3_PktSteeringInput; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_PktSteeringFilterConf { + uint8_t version; + uint8_t priority; + Vmxnet3_PktSteeringActionData actionData; + Vmxnet3_PktSteeringInput spec; + Vmxnet3_PktSteeringInput mask; + uint8_t pad[4]; +} +#include "vmware_pack_end.h" +Vmxnet3_PktSteeringFilterConf; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_PktSteeringVerInfo { + uint8_t version; + uint8_t pad; + uint16_t maxMasks; + uint32_t maxFilters; +} +#include "vmware_pack_end.h" +Vmxnet3_PktSteeringVerInfo; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_PktSteeringFilterStats { + uint64_t packets; +} +#include "vmware_pack_end.h" +Vmxnet3_PktSteeringFilterStats; + +typedef enum { + VMXNET3_PKTSTEERING_CMD_GET_VER = 0x0, /* start of GET commands */ + VMXNET3_PKTSTEERING_CMD_GET_FILTER_STATS, + + VMXNET3_PKTSTEERING_CMD_ADD_FILTER = 0x80, /*start of SET commands */ + VMXNET3_PKTSTEERING_CMD_DEL_FILTER, + VMXNET3_PKTSTEERING_CMD_FLUSH, +} Vmxnet3_PktSteeringCmd; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_PktSteeringCmdMsg { + uint16_t cmd; /* enum Vmxnet3PktSteeringCmd */ + uint16_t msgSize; + uint32_t outputLen; + uint64_t outputPA; + Vmxnet3_PktSteeringFilterConf fConf; +} +#include "vmware_pack_end.h" +Vmxnet3_PktSteeringCmdMsg; + #define VMXNET3_PM_MAX_FILTERS 6 #define VMXNET3_PM_MAX_PATTERN_SIZE 128 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) @@ -736,8 +901,16 @@ struct Vmxnet3_MemoryRegion { #include "vmware_pack_end.h" Vmxnet3_MemoryRegion; +/* + * Assume each queue can have upto 16 memory region + * we have 8 + 8 = 16 queues. So max regions is + * defined as 16 * 16 + * when more region is passed to backend, the handling + * is undefined, Backend can choose to fail the the request + * or ignore the extra region. + */ #define MAX_MEMORY_REGION_PER_QUEUE 16 -#define MAX_MEMORY_REGION_PER_DEVICE 256 +#define MAX_MEMORY_REGION_PER_DEVICE (16 * 16) typedef #include "vmware_pack_begin.h" @@ -749,15 +922,36 @@ struct Vmxnet3_MemRegs { #include "vmware_pack_end.h" Vmxnet3_MemRegs; +typedef enum Vmxnet3_RSSField { + VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001, + VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002, + VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004, + VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008, + VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010, + VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020, +} Vmxnet3_RSSField; + +typedef +#include "vmware_pack_begin.h" +struct Vmxnet3_EncapDstPort { + __le16 geneveDstPort; + __le16 vxlanDstPort; +} +#include "vmware_pack_end.h" +Vmxnet3_EncapDstPort; + /* - * If the command data <= 16 bytes, use the shared memory direcly. - * Otherwise, use the variable length configuration descriptor. + * If a command data does not exceed 16 bytes, it can use + * the shared memory directly. Otherwise use variable length + * configuration descriptor to pass the data. */ typedef #include "vmware_pack_begin.h" union Vmxnet3_CmdInfo { Vmxnet3_VariableLenConfDesc varConf; Vmxnet3_SetPolling setPolling; + Vmxnet3_RSSField setRSSFields; + Vmxnet3_EncapDstPort encapDstPort; __le64 data[2]; } #include "vmware_pack_end.h"