From patchwork Sun Apr 14 11:11:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Kumar Sharma X-Patchwork-Id: 52757 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D254856A1; Sun, 14 Apr 2019 13:12:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 934084D27; Sun, 14 Apr 2019 13:12:01 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3EBAEQT011334; Sun, 14 Apr 2019 04:12:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0818; bh=j7YjBdqO2o3fg2PvEWx6Imo6nnVxRwGqZKp/zHV0yzE=; b=lK1ooOCz+x1u1YH82UxlndPxGOLW51bgXOBIckzhlrU3LXbZpfKxo4x/fa+eC1TL1FpI bmYCP0SwOlyg0G6oiRv2UfALLZy1fT2B4MhN+6nnYfUhJuqUDhTraWcsFaw6+wLkEJ4V Z4fiLrG47zGz66m/J6Ew5cDQUyCUCZ6taZcV7lcZbtDfTVzQQpRM7LEcALunO1FaQ+ZF +FdOf4Ki39OOewcJ08MxIMdfcV/wkMaHtSYRLsl/JPjTgQtxTmVxpeOvu/pk1LzMxl4S qHGcFAr32yAKego7tAtzLW1kwa+uw0w8wLi0WpOqANioctmGSn7Y7fvkufqDnAgMnGNe Hw== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2ruf9jtpc9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 14 Apr 2019 04:12:00 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 14 Apr 2019 04:11:59 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sun, 14 Apr 2019 04:11:59 -0700 Received: from dell-e5540.caveonetworks.com (unknown [10.29.16.81]) by maili.marvell.com (Postfix) with ESMTP id 4D1D13F703F; Sun, 14 Apr 2019 04:11:53 -0700 (PDT) From: To: CC: , , , Vivek Sharma , Date: Sun, 14 Apr 2019 16:41:42 +0530 Message-ID: <1555240302-9771-1-git-send-email-viveksharma@marvell.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-14_02:, , signatures=0 Subject: [dpdk-dev] [PATCH] ethdev: fix QinQ strip offload support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vivek Sharma Enable missing support for QinQ strip rx offload in vlan offload set/get methods. Fixes: cc9d0456b870 ("i40e: support double vlan stripping and insertion") Cc: stable@dpdk.org Signed-off-by: Vivek Sharma --- lib/librte_ethdev/rte_ethdev.c | 17 +++++++++++++++++ lib/librte_ethdev/rte_ethdev.h | 5 ++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethdev.c index 243beb4..222df4e 100644 --- a/lib/librte_ethdev/rte_ethdev.c +++ b/lib/librte_ethdev/rte_ethdev.c @@ -2770,6 +2770,19 @@ rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask) mask |= ETH_VLAN_EXTEND_MASK; } + cur = !!(offload_mask & ETH_QINQ_STRIP_OFFLOAD); + org = !!(dev->data->dev_conf.rxmode.offloads & + DEV_RX_OFFLOAD_QINQ_STRIP); + if (cur != org) { + if (cur) + dev->data->dev_conf.rxmode.offloads |= + DEV_RX_OFFLOAD_QINQ_STRIP; + else + dev->data->dev_conf.rxmode.offloads &= + ~DEV_RX_OFFLOAD_QINQ_STRIP; + mask |= ETH_QINQ_STRIP_MASK; + } + /*no change*/ if (mask == 0) return ret; @@ -2805,6 +2818,10 @@ rte_eth_dev_get_vlan_offload(uint16_t port_id) DEV_RX_OFFLOAD_VLAN_EXTEND) ret |= ETH_VLAN_EXTEND_OFFLOAD; + if (dev->data->dev_conf.rxmode.offloads & + DEV_RX_OFFLOAD_QINQ_STRIP) + ret |= DEV_RX_OFFLOAD_QINQ_STRIP; + return ret; } diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h index 40a068f..c1792f4 100644 --- a/lib/librte_ethdev/rte_ethdev.h +++ b/lib/librte_ethdev/rte_ethdev.h @@ -550,11 +550,13 @@ struct rte_eth_rss_conf { #define ETH_VLAN_STRIP_OFFLOAD 0x0001 /**< VLAN Strip On/Off */ #define ETH_VLAN_FILTER_OFFLOAD 0x0002 /**< VLAN Filter On/Off */ #define ETH_VLAN_EXTEND_OFFLOAD 0x0004 /**< VLAN Extend On/Off */ +#define ETH_QINQ_STRIP_OFFLOAD 0x0008 /**< QINQ Strip On/Off */ /* Definitions used for mask VLAN setting */ #define ETH_VLAN_STRIP_MASK 0x0001 /**< VLAN Strip setting mask */ #define ETH_VLAN_FILTER_MASK 0x0002 /**< VLAN Filter setting mask*/ #define ETH_VLAN_EXTEND_MASK 0x0004 /**< VLAN Extend setting mask*/ +#define ETH_QINQ_STRIP_MASK 0x0008 /**< QINQ Strip setting mask */ #define ETH_VLAN_ID_MAX 0x0FFF /**< VLAN ID is in lower 12 bits*/ /* Definitions used for receive MAC address */ @@ -965,7 +967,8 @@ struct rte_eth_conf { DEV_RX_OFFLOAD_TCP_CKSUM) #define DEV_RX_OFFLOAD_VLAN (DEV_RX_OFFLOAD_VLAN_STRIP | \ DEV_RX_OFFLOAD_VLAN_FILTER | \ - DEV_RX_OFFLOAD_VLAN_EXTEND) + DEV_RX_OFFLOAD_VLAN_EXTEND | \ + DEV_RX_OFFLOAD_QINQ_STRIP) /* * If new Rx offload capabilities are defined, they also must be