[1/2] build: shorten code for instruction set detection

Message ID 20190514133702.2993-1-bruce.richardson@intel.com
State New
Delegated to: Thomas Monjalon
Headers show
Series
  • [1/2] build: shorten code for instruction set detection
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Checks

Context Check Description
ci/intel-Performance-Testing success Performance Testing PASS
ci/mellanox-Performance-Testing success Performance Testing PASS
ci/checkpatch success coding style OK

Commit Message

Bruce Richardson May 14, 2019, 1:37 p.m.
Rather than checking flag by flag individually, use a loop to make it
easier to check new flags.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
 config/x86/meson.build | 34 +++++++++++++---------------------
 1 file changed, 13 insertions(+), 21 deletions(-)

Patch

diff --git a/config/x86/meson.build b/config/x86/meson.build
index bb23771b4..a650a1ca8 100644
--- a/config/x86/meson.build
+++ b/config/x86/meson.build
@@ -28,6 +28,19 @@  foreach f:base_flags
 	compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
 endforeach
 
+optional_flags = ['AES', 'PCLMUL',
+		'AVX', 'AVX2', 'AVX512F']
+foreach f:optional_flags
+	if cc.get_define('__@0@__'.format(f), args: machine_args) == '1'
+		if f == 'PCLMUL' # special case flags with different defines
+			f = 'PCLMULQDQ'
+		endif
+		dpdk_conf.set('RTE_MACHINE_CPUFLAG_' + f, 1)
+		compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
+	endif
+endforeach
+
+
 dpdk_conf.set('RTE_ARCH_X86', 1)
 if dpdk_conf.get('RTE_ARCH_64')
 	dpdk_conf.set('RTE_ARCH_X86_64', 1)
@@ -37,25 +50,4 @@  else
 	dpdk_conf.set('RTE_ARCH', 'i686')
 endif
 
-if cc.get_define('__AES__', args: machine_args) != ''
-	dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1)
-	compile_time_cpuflags += ['RTE_CPUFLAG_AES']
-endif
-if cc.get_define('__PCLMUL__', args: machine_args) != ''
-	dpdk_conf.set('RTE_MACHINE_CPUFLAG_PCLMULQDQ', 1)
-	compile_time_cpuflags += ['RTE_CPUFLAG_PCLMULQDQ']
-endif
-if cc.get_define('__AVX__', args: machine_args) != ''
-	dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX', 1)
-	compile_time_cpuflags += ['RTE_CPUFLAG_AVX']
-endif
-if cc.get_define('__AVX2__', args: machine_args) != ''
-	dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX2', 1)
-	compile_time_cpuflags += ['RTE_CPUFLAG_AVX2']
-endif
-if cc.get_define('__AVX512F__', args: machine_args) != ''
-	dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX512F', 1)
-	compile_time_cpuflags += ['RTE_CPUFLAG_AVX512F']
-endif
-
 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)