[v1,1/9] raw/octeontx2_dma: add build infra and device probe
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Commit Message
From: Satha Rao <skoteshwar@marvell.com>
Add the make and meson based build infrastructure along
with the DMA device probe.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
---
config/common_base | 5 +
drivers/raw/Makefile | 1 +
drivers/raw/meson.build | 2 +-
drivers/raw/octeontx2_dma/Makefile | 31 ++++++
drivers/raw/octeontx2_dma/meson.build | 18 ++++
drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 102 ++++++++++++++++++
.../rte_pmd_octeontx2_dma_version.map | 4 +
mk/rte.app.mk | 1 +
8 files changed, 163 insertions(+), 1 deletion(-)
create mode 100644 drivers/raw/octeontx2_dma/Makefile
create mode 100644 drivers/raw/octeontx2_dma/meson.build
create mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
create mode 100644 drivers/raw/octeontx2_dma/rte_pmd_octeontx2_dma_version.map
Comments
On Sat, 2019-06-01 at 23:50 +0530, jerinj@marvell.com wrote:
> diff --git a/drivers/raw/octeontx2_dma/meson.build
> b/drivers/raw/octeontx2_dma/meson.build
> new file mode 100644
> index 000000000..1281268aa
> --- /dev/null
> +++ b/drivers/raw/octeontx2_dma/meson.build
> @@ -0,0 +1,18 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(C) 2019 Marvell International Ltd.
> +#
> +
> +deps += ['rawdev', 'ring', 'kvargs', 'bus_pci', 'common_octeontx2',
> 'mempool_octeontx2']
> +sources = files('otx2_dpi_rawdev.c')
> +
> +extra_flags = []
> +# This integrated controller runs only on a arm64 machine, remove
> 32bit warnings
> +if not dpdk_conf.get('RTE_ARCH_64')
> + extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-
> int-cast']
> +endif
> +
> +foreach flag: extra_flags
> + if cc.has_argument(flag)
> + cflags += flag
> + endif
> +endforeach
If it only works on 64bit, shouldn't the build be disabled for 32bit
targets?
> -----Original Message-----
> From: Luca Boccassi <bluca@debian.org>
> Sent: Monday, June 3, 2019 4:48 PM
> To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; dev@dpdk.org
> Cc: Satha Koteswara Rao Kottidi <skoteshwar@marvell.com>; Vamsi Krishna
> Attunuru <vattunuru@marvell.com>
> Subject: Re: [dpdk-dev] [PATCH v1 1/9] raw/octeontx2_dma: add build infra
> and device probe
>
> On Sat, 2019-06-01 at 23:50 +0530, jerinj@marvell.com wrote:
> > diff --git a/drivers/raw/octeontx2_dma/meson.build
> > b/drivers/raw/octeontx2_dma/meson.build
> > new file mode 100644
> > index 000000000..1281268aa
> > --- /dev/null
> > +++ b/drivers/raw/octeontx2_dma/meson.build
> > @@ -0,0 +1,18 @@
> > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(C) 2019 Marvell
> > +International Ltd.
> > +#
> > +
> > +deps += ['rawdev', 'ring', 'kvargs', 'bus_pci', 'common_octeontx2',
> > 'mempool_octeontx2']
> > +sources = files('otx2_dpi_rawdev.c')
> > +
> > +extra_flags = []
> > +# This integrated controller runs only on a arm64 machine, remove
> > 32bit warnings
> > +if not dpdk_conf.get('RTE_ARCH_64')
> > + extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-
> > int-cast']
> > +endif
> > +
> > +foreach flag: extra_flags
> > + if cc.has_argument(flag)
> > + cflags += flag
> > + endif
> > +endforeach
>
> If it only works on 64bit, shouldn't the build be disabled for 32bit targets?
We just thought of enabling it for 32bit to _detect_ build regression for 32bit so
that in future we can run with ILP32 if required.
If you have strong option on this then we can disable it if required.
>
> --
> Kind regards,
> Luca Boccassi
On Thu, 2019-06-06 at 08:32 +0000, Jerin Jacob Kollanukkaran wrote:
> > -----Original Message-----
> > From: Luca Boccassi <
> > bluca@debian.org
> > >
> > Sent: Monday, June 3, 2019 4:48 PM
> > To: Jerin Jacob Kollanukkaran <
> > jerinj@marvell.com
> > >;
> > dev@dpdk.org
> >
> > Cc: Satha Koteswara Rao Kottidi <
> > skoteshwar@marvell.com
> > >; Vamsi Krishna
> > Attunuru <
> > vattunuru@marvell.com
> > >
> > Subject: Re: [dpdk-dev] [PATCH v1 1/9] raw/octeontx2_dma: add build
> > infra
> > and device probe
> >
> > On Sat, 2019-06-01 at 23:50 +0530,
> > jerinj@marvell.com
> > wrote:
> > > diff --git a/drivers/raw/octeontx2_dma/meson.build
> > > b/drivers/raw/octeontx2_dma/meson.build
> > > new file mode 100644
> > > index 000000000..1281268aa
> > > --- /dev/null
> > > +++ b/drivers/raw/octeontx2_dma/meson.build
> > > @@ -0,0 +1,18 @@
> > > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(C) 2019
> > > Marvell
> > > +International Ltd.
> > > +#
> > > +
> > > +deps += ['rawdev', 'ring', 'kvargs', 'bus_pci',
> > > 'common_octeontx2',
> > > 'mempool_octeontx2']
> > > +sources = files('otx2_dpi_rawdev.c')
> > > +
> > > +extra_flags = []
> > > +# This integrated controller runs only on a arm64 machine,
> > > remove
> > > 32bit warnings
> > > +if not dpdk_conf.get('RTE_ARCH_64')
> > > + extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-
> > > pointer-to-
> > > int-cast']
> > > +endif
> > > +
> > > +foreach flag: extra_flags
> > > + if cc.has_argument(flag)
> > > + cflags += flag
> > > + endif
> > > +endforeach
> >
> > If it only works on 64bit, shouldn't the build be disabled for
> > 32bit targets?
>
> We just thought of enabling it for 32bit to _detect_ build regression
> for 32bit so
> that in future we can run with ILP32 if required.
>
> If you have strong option on this then we can disable it if required.
No it's fine, it was just an observation.
@@ -741,6 +741,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=n
#
CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y
+#
+# Compile PMD for octeontx2 DMA device
+#
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV=y
+
#
# Compile librte_ring
#
@@ -10,5 +10,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_CMDIF_RAWDEV) += dpaa2_cmdif
DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV) += dpaa2_qdma
endif
DIRS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += ifpga_rawdev
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += octeontx2_dma
include $(RTE_SDK)/mk/rte.subdir.mk
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright 2018 NXP
-drivers = ['skeleton_rawdev', 'dpaa2_cmdif', 'dpaa2_qdma', 'ifpga_rawdev']
+drivers = ['skeleton_rawdev', 'dpaa2_cmdif', 'dpaa2_qdma', 'ifpga_rawdev', 'octeontx2_dma']
std_deps = ['rawdev']
config_flag_fmt = 'RTE_LIBRTE_PMD_@0@_RAWDEV'
driver_name_fmt = 'rte_pmd_@0@'
new file mode 100644
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2019 Marvell International Ltd.
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_octeontx2_dma.a
+
+CFLAGS += -DALLOW_EXPERIMENTAL_API -O3 $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2/
+CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2/
+CFLAGS += -I$(RTE_SDK)/drivers/raw/octeontx2_dma/
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring -lrte_rawdev
+LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci
+
+ifneq ($(CONFIG_RTE_ARCH_64),y)
+CFLAGS += -Wno-int-to-pointer-cast
+CFLAGS += -Wno-pointer-to-int-cast
+endif
+
+EXPORT_MAP := rte_pmd_octeontx2_dma_version.map
+
+LIBABIVER := 1
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += otx2_dpi_rawdev.c
+
+include $(RTE_SDK)/mk/rte.lib.mk
new file mode 100644
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2019 Marvell International Ltd.
+#
+
+deps += ['rawdev', 'ring', 'kvargs', 'bus_pci', 'common_octeontx2', 'mempool_octeontx2']
+sources = files('otx2_dpi_rawdev.c')
+
+extra_flags = []
+# This integrated controller runs only on a arm64 machine, remove 32bit warnings
+if not dpdk_conf.get('RTE_ARCH_64')
+ extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
+endif
+
+foreach flag: extra_flags
+ if cc.has_argument(flag)
+ cflags += flag
+ endif
+endforeach
new file mode 100644
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include <string.h>
+#include <unistd.h>
+
+#include <rte_bus.h>
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_devargs.h>
+#include <rte_eal.h>
+#include <rte_errno.h>
+#include <rte_log.h>
+#include <rte_pci.h>
+#include <rte_per_lcore.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <otx2_mempool.h>
+
+static const struct rte_pci_id pci_dma_map[] = {
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVID_OCTEONTX2_DPI_VF)
+ },
+ {
+ .vendor_id = 0,
+ },
+};
+
+static int
+otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *pci_dev)
+{
+ char name[RTE_RAWDEV_NAME_MAX_LEN];
+ struct rte_rawdev *rawdev;
+
+ /* For secondary processes, the primary has done all the work */
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
+ if (pci_dev->mem_resource[0].addr == NULL) {
+ otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr,
+ pci_dev->mem_resource[2].addr);
+ return -ENODEV;
+ }
+
+ memset(name, 0, sizeof(name));
+ snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
+ pci_dev->addr.bus, pci_dev->addr.devid,
+ pci_dev->addr.function);
+
+ /* Allocate device structure */
+ rawdev = rte_rawdev_pmd_allocate(name, 0, rte_socket_id());
+ if (rawdev == NULL) {
+ otx2_err("Rawdev allocation failed");
+ return -EINVAL;
+ }
+
+ rawdev->device = &pci_dev->device;
+ rawdev->driver_name = pci_dev->driver->driver.name;
+
+ return 0;
+}
+
+static int
+otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+ char name[RTE_RAWDEV_NAME_MAX_LEN];
+ struct rte_rawdev *rawdev;
+
+ if (pci_dev == NULL) {
+ otx2_dpi_dbg("Invalid pci_dev of the device!");
+ return -EINVAL;
+ }
+
+ memset(name, 0, sizeof(name));
+ snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
+ pci_dev->addr.bus, pci_dev->addr.devid,
+ pci_dev->addr.function);
+
+ rawdev = rte_rawdev_pmd_get_named_dev(name);
+ if (rawdev == NULL) {
+ otx2_dpi_dbg("Invalid device name (%s)", name);
+ return -EINVAL;
+ }
+
+ /* rte_rawdev_close is called by pmd_release */
+ return rte_rawdev_pmd_release(rawdev);
+}
+
+static struct rte_pci_driver rte_dpi_rawdev_pmd = {
+ .id_table = pci_dma_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
+ .probe = otx2_dpi_rawdev_probe,
+ .remove = otx2_dpi_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(dpi_rawdev_pci_driver, rte_dpi_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(dpi_rawdev_pci_driver, pci_dma_map);
+RTE_PMD_REGISTER_KMOD_DEP(dpi_rawdev_pci_driver, "vfio-pci");
new file mode 100644
@@ -0,0 +1,4 @@
+DPDK_19.05 {
+
+ local: *;
+};
@@ -309,6 +309,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_IFPGA_BUS),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += -lrte_pmd_ifpga_rawdev
_LDLIBS-$(CONFIG_RTE_LIBRTE_IPN3KE_PMD) += -lrte_pmd_ipn3ke
endif # CONFIG_RTE_LIBRTE_IFPGA_BUS
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += -lrte_pmd_octeontx2_dma
endif # CONFIG_RTE_LIBRTE_RAWDEV
endif # !CONFIG_RTE_BUILD_SHARED_LIBS