From: Gautam Dawar <gdawar@solarflare.com>
Set WORKAROUND_BUG26807 which does the job.
Fix the misunderstanding in the Medford code: i.e. the workaround is
always supported by firmware, but the driver still needs to enable it.
Also, as it now applies to all EF10 controllers, the implementation is
moved to EF10 common place.
Fixes: 94190e3543bf ("net/sfc/base: import SFN8xxx family support")
Fixes: 2b38e7b7b7e1 ("net/sfc/base: add Medford2 support to NIC module")
Cc: stable@dpdk.org
Signed-off-by: Gautam Dawar <gdawar@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nic.c | 57 ++++++++++++++++++++++++++++++++++++-
drivers/net/sfc/base/hunt_nic.c | 41 ++------------------------
drivers/net/sfc/base/medford2_nic.c | 3 --
drivers/net/sfc/base/medford_nic.c | 3 --
4 files changed, 58 insertions(+), 46 deletions(-)
@@ -1753,6 +1753,56 @@
}
static __checkReturn efx_rc_t
+ef10_set_workaround_bug26807(
+ __in efx_nic_t *enp)
+{
+ efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+ uint32_t flags;
+ efx_rc_t rc;
+
+ /*
+ * If the bug26807 workaround is enabled, then firmware has enabled
+ * support for chained multicast filters. Firmware will reset (FLR)
+ * functions which have filters in the hardware filter table when the
+ * workaround is enabled/disabled.
+ *
+ * We must recheck if the workaround is enabled after inserting the
+ * first hardware filter, in case it has been changed since this check.
+ */
+ rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
+ B_TRUE, &flags);
+ if (rc == 0) {
+ encp->enc_bug26807_workaround = B_TRUE;
+ if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
+ /*
+ * Other functions had installed filters before the
+ * workaround was enabled, and they have been reset
+ * by firmware.
+ */
+ EFSYS_PROBE(bug26807_workaround_flr_done);
+ /* FIXME: bump MC warm boot count ? */
+ }
+ } else if (rc == EACCES) {
+ /*
+ * Unprivileged functions cannot enable the workaround in older
+ * firmware.
+ */
+ encp->enc_bug26807_workaround = B_FALSE;
+ } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
+ encp->enc_bug26807_workaround = B_FALSE;
+ } else {
+ goto fail1;
+ }
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+static __checkReturn efx_rc_t
ef10_nic_board_cfg(
__in efx_nic_t *enp)
{
@@ -1910,13 +1960,18 @@
goto fail10;
encp->enc_privilege_mask = mask;
+ if ((rc = ef10_set_workaround_bug26807(enp)) != 0)
+ goto fail11;
+
/* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)
if (rc != EACCES)
- goto fail11;
+ goto fail12;
return (0);
+fail12:
+ EFSYS_PROBE(fail12);
fail11:
EFSYS_PROBE(fail11);
fail10:
@@ -72,7 +72,6 @@
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
efx_port_t *epp = &(enp->en_port);
- uint32_t flags;
uint32_t sysclk, dpcpu_clk;
uint32_t bandwidth;
efx_rc_t rc;
@@ -130,43 +129,9 @@
encp->enc_bug41750_workaround = B_TRUE;
}
- /*
- * If the bug26807 workaround is enabled, then firmware has enabled
- * support for chained multicast filters. Firmware will reset (FLR)
- * functions which have filters in the hardware filter table when the
- * workaround is enabled/disabled.
- *
- * We must recheck if the workaround is enabled after inserting the
- * first hardware filter, in case it has been changed since this check.
- */
- rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
- B_TRUE, &flags);
- if (rc == 0) {
- encp->enc_bug26807_workaround = B_TRUE;
- if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
- /*
- * Other functions had installed filters before the
- * workaround was enabled, and they have been reset
- * by firmware.
- */
- EFSYS_PROBE(bug26807_workaround_flr_done);
- /* FIXME: bump MC warm boot count ? */
- }
- } else if (rc == EACCES) {
- /*
- * Unprivileged functions cannot enable the workaround in older
- * firmware.
- */
- encp->enc_bug26807_workaround = B_FALSE;
- } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
- encp->enc_bug26807_workaround = B_FALSE;
- } else {
- goto fail3;
- }
-
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
- goto fail4;
+ goto fail3;
/*
* The Huntington timer quantum is 1536 sysclk cycles, documented for
@@ -215,7 +180,7 @@
encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
- goto fail5;
+ goto fail4;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
/* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -223,8 +188,6 @@
return (0);
-fail5:
- EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
fail3:
@@ -69,9 +69,6 @@
encp->enc_bug41750_workaround = B_TRUE;
}
- /* Chained multicast is always enabled on Medford2 */
- encp->enc_bug26807_workaround = B_TRUE;
-
/*
* If the bug61265 workaround is enabled, then interrupt holdoff timers
* cannot be controlled by timer table writes, so MCDI must be used
@@ -67,9 +67,6 @@
encp->enc_bug41750_workaround = B_TRUE;
}
- /* Chained multicast is always enabled on Medford */
- encp->enc_bug26807_workaround = B_TRUE;
-
/*
* If the bug61265 workaround is enabled, then interrupt holdoff timers
* cannot be controlled by timer table writes, so MCDI must be used