From patchwork Tue Jun 11 15:51:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leyi Rong X-Patchwork-Id: 54691 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 570241C561; Tue, 11 Jun 2019 17:54:57 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 849451C4EA for ; Tue, 11 Jun 2019 17:54:17 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jun 2019 08:54:17 -0700 X-ExtLoop1: 1 Received: from lrong-srv-03.sh.intel.com ([10.67.119.177]) by orsmga001.jf.intel.com with ESMTP; 11 Jun 2019 08:54:16 -0700 From: Leyi Rong To: qi.z.zhang@intel.com Cc: dev@dpdk.org, Leyi Rong Date: Tue, 11 Jun 2019 23:51:47 +0800 Message-Id: <20190611155221.2703-33-leyi.rong@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190611155221.2703-1-leyi.rong@intel.com> References: <20190604054248.68510-1-leyi.rong@intel.com> <20190611155221.2703-1-leyi.rong@intel.com> Subject: [dpdk-dev] [PATCH v2 32/66] net/ice/base: add rd64 support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add API support for rd64. Signed-off-by: Qi Zhang Signed-off-by: Leyi Rong --- drivers/net/ice/base/ice_osdep.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h index ede893fc9..35a17b941 100644 --- a/drivers/net/ice/base/ice_osdep.h +++ b/drivers/net/ice/base/ice_osdep.h @@ -126,11 +126,19 @@ do { \ #define ICE_PCI_REG(reg) rte_read32(reg) #define ICE_PCI_REG_ADDR(a, reg) \ ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) +#define ICE_PCI_REG64(reg) rte_read64(reg) +#define ICE_PCI_REG_ADDR64(a, reg) \ + ((volatile uint64_t *)((char *)(a)->hw_addr + (reg))) static inline uint32_t ice_read_addr(volatile void *addr) { return rte_le_to_cpu_32(ICE_PCI_REG(addr)); } +static inline uint64_t ice_read_addr64(volatile void *addr) +{ + return rte_le_to_cpu_64(ICE_PCI_REG64(addr)); +} + #define ICE_PCI_REG_WRITE(reg, value) \ rte_write32((rte_cpu_to_le_32(value)), reg) @@ -145,6 +153,7 @@ static inline uint32_t ice_read_addr(volatile void *addr) ICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((a), (reg)), (value)) #define flush(a) ice_read_addr(ICE_PCI_REG_ADDR((a), (GLGEN_STAT))) #define div64_long(n, d) ((n) / (d)) +#define rd64(a, reg) ice_read_addr64(ICE_PCI_REG_ADDR64((a), (reg))) #define BITS_PER_BYTE 8