From patchwork Thu Aug 8 08:22:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57561 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1413834F2; Thu, 8 Aug 2019 10:23:09 +0200 (CEST) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by dpdk.org (Postfix) with ESMTP id 715E5276C for ; Thu, 8 Aug 2019 10:22:57 +0200 (CEST) Received: by mail-wr1-f67.google.com with SMTP id b3so1596319wro.4 for ; Thu, 08 Aug 2019 01:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=0GlbaRdccY54BFN5ZohRBC0g+CI7Vg9FEOu0cE4CYKM=; b=RlfGjRAG24JbrFWtkFWGwuCGAj2F3AUO1voLnHqpEE/SVP3STQeKPMolMsc/fOiX26 rEHAaurMZ5o4k1s/qtPw0GtjHlYFpg7Uz3cNFSbNwur/o3AezIWseTGh4oNqaOBMYECR 4LyGKRo7CDZd1/REfV4di0uGOthGM5J1m2MwIi51eCdxnuHpnB6dCh6bZ+2ulEbO0OAN v5BROrpNnqDo042G7IAtCfeyT+bwgPOpIV0jaqZsTwuE+/RA85Q8BFL3Ze0HQAQOBoWp YsL/lQN7MTe3/gbLK8NCgO9cl7BxhOzSoVHUnW1822eyloPusWAMnJKwyWvbK2srfeCc aFHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=0GlbaRdccY54BFN5ZohRBC0g+CI7Vg9FEOu0cE4CYKM=; b=cp2gR4VQaOc3dlYcmoOAccidivMHLVsWJ90wIBC5hjcDMjPsl9kXy9oX1CFLqZYgox 8EKUQy2qTovOUCXbdpd02BY+0NWiHgqu63D8CR7m/kF5xBDE4SHz+r7Vm8BzyR8eKfI+ LCDkHk/dRhE8PakWoyLXeBoMmU69LBmI4v3gT/lQap6gV1S34lJrA9zukiLuLcuV1r1m 920iPV4ZoMtvpugL3Yxsc87t2kbF2edQOi8Q7OVKN/7ZtSUMmIzkqXQh1rFtjVwzGzAd 3ObaA/+IKchWTsth5ATqcvRWz6fLAjvBb9m4h8yDzlJkRNnA1ZOa1iTKzkcjN7Hyvox7 Cn9w== X-Gm-Message-State: APjAAAWzNIb+lUqcRGcFTjjkHlQlLcpQdiKAubKQm/P78i1JZRCgozow GRUiBdPNgcYBbD73HPh5UNWBnnq7pQ== X-Google-Smtp-Source: APXvYqyAwHBzrH77dNHsxUb5bFSwesU8lsOW7tYNU1OYAK5BUpduSZ8bcoMvpdqW84ebkUeEhDcbCw== X-Received: by 2002:adf:ea4c:: with SMTP id j12mr16098540wrn.75.1565252576982; Thu, 08 Aug 2019 01:22:56 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id t13sm111437018wrr.0.2019.08.08.01.22.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Aug 2019 01:22:56 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Thu, 8 Aug 2019 10:22:11 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V3 06/12] net/i40e: fix Tx descriptor status api X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. As before, we still need to take care about only checking descriptors that have the RS bit. Additionally, we can avoid an access to the ring if offset is greater or equal to nb_tx_desc - nb_tx_free. Fixes: a9dd9af6f38e ("net/i40e: implement descriptor status API") Cc: stable@dpdk.org Signed-off-by: Olivier Matz --- drivers/net/i40e/i40e_rxtx.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 692c3bab4b5f..d84a97732f1e 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -2031,22 +2031,39 @@ i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) struct i40e_tx_queue *txq = tx_queue; volatile uint64_t *status; uint64_t mask, expect; - uint32_t desc; + int32_t desc, dd; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; + if (offset >= txq->nb_tx_desc - txq->nb_tx_free) + return RTE_ETH_TX_DESC_DONE; + + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; - desc = txq->tx_tail + offset; - /* go to next desc that has the RS bit */ - desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * - txq->tx_rs_thresh; - if (desc >= txq->nb_tx_desc) { - desc -= txq->nb_tx_desc; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + /* offset is too small, no other way than reading PCI reg */ + if (unlikely(offset < txq->tx_rs_thresh)) { + int16_t tx_head, queue_size; + tx_head = I40E_READ_REG(I40E_VSI_TO_HW(txq->vsi), + I40E_QTX_HEAD(txq->reg_idx)); + queue_size = txq->tx_tail - tx_head; + if (queue_size < 0) + queue_size += txq->nb_tx_desc; + return queue_size > offset ? RTE_ETH_TX_DESC_FULL : + RTE_ETH_TX_DESC_DONE; } - status = &txq->tx_ring[desc].cmd_type_offset_bsz; + /* index of the dd bit to look at */ + dd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1; + + /* In full featured mode, RS bit is only set in the last descriptor */ + /* of a multisegments packet */ + if (!(txq->offloads == 0 && + txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) + dd = txq->sw_ring[dd].last_id; + + status = &txq->tx_ring[dd].cmd_type_offset_bsz; mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK); expect = rte_cpu_to_le_64( I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);