common/cpt: add support for new firmware
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Commit Message
From: Ankur Dwivedi <adwivedi@marvell.com>
With the latest firmware, there are few changes for zuc and snow3g.
1. The iv_source is present in bitfield 7 of minor opcode. In the
old firmware this was present in bitfield 6.
2. Algorithm type is a 2 bit field in new firmware. In the old
firmware it was named as cipher type and it was a 1 bit field.
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
drivers/common/cpt/cpt_mcode_defines.h | 4 ++--
drivers/common/cpt/cpt_ucode.h | 6 ++++--
2 files changed, 6 insertions(+), 4 deletions(-)
Comments
Hi Akhil, Pablo,
From my end, this patch is good to go.
Thanks,
Anoob
> -----Original Message-----
> From: Anoob Joseph <anoobj@marvell.com>
> Sent: Wednesday, August 14, 2019 3:11 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>; Pablo de Lara
> <pablo.de.lara.guarch@intel.com>
> Cc: Ankur Dwivedi <adwivedi@marvell.com>; Jerin Jacob Kollanukkaran
> <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; dev@dpdk.org; Anoob Joseph
> <anoobj@marvell.com>
> Subject: [PATCH] common/cpt: add support for new firmware
>
> From: Ankur Dwivedi <adwivedi@marvell.com>
>
> With the latest firmware, there are few changes for zuc and snow3g.
>
> 1. The iv_source is present in bitfield 7 of minor opcode. In the old firmware this
> was present in bitfield 6.
>
> 2. Algorithm type is a 2 bit field in new firmware. In the old firmware it was
> named as cipher type and it was a 1 bit field.
>
> Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
> Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> ---
> drivers/common/cpt/cpt_mcode_defines.h | 4 ++--
> drivers/common/cpt/cpt_ucode.h | 6 ++++--
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/common/cpt/cpt_mcode_defines.h
> b/drivers/common/cpt/cpt_mcode_defines.h
> index c0adbd5..b7c3feb 100644
> --- a/drivers/common/cpt/cpt_mcode_defines.h
> +++ b/drivers/common/cpt/cpt_mcode_defines.h
> @@ -303,8 +303,8 @@ struct cpt_ctx {
> uint64_t hmac :1;
> uint64_t zsk_flags :3;
> uint64_t k_ecb :1;
> - uint64_t snow3g :1;
> - uint64_t rsvd :22;
> + uint64_t snow3g :2;
> + uint64_t rsvd :21;
> /* Below fields are accessed by hardware */
> union {
> mc_fc_context_t fctx;
> diff --git a/drivers/common/cpt/cpt_ucode.h
> b/drivers/common/cpt/cpt_ucode.h index 7d9c31e..0dac12e 100644
> --- a/drivers/common/cpt/cpt_ucode.h
> +++ b/drivers/common/cpt/cpt_ucode.h
> @@ -1467,7 +1467,8 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
> opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
>
> /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
> - opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
> +
> + opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
> (0 << 3) | (flags & 0x7));
>
> if (flags == 0x1) {
> @@ -1791,7 +1792,8 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
> opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
>
> /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
> - opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
> +
> + opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
> (0 << 3) | (flags & 0x7));
>
> /* consider iv len */
> --
> 2.7.4
>
> Hi Akhil, Pablo,
>
> From my end, this patch is good to go.
>
> Thanks,
> Anoob
>
> > -----Original Message-----
> > From: Anoob Joseph <anoobj@marvell.com>
> > Sent: Wednesday, August 14, 2019 3:11 PM
> > To: Akhil Goyal <akhil.goyal@nxp.com>; Pablo de Lara
> > <pablo.de.lara.guarch@intel.com>
> > Cc: Ankur Dwivedi <adwivedi@marvell.com>; Jerin Jacob Kollanukkaran
> > <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> > <pathreya@marvell.com>; dev@dpdk.org; Anoob Joseph
> > <anoobj@marvell.com>
> > Subject: [PATCH] common/cpt: add support for new firmware
> >
> > From: Ankur Dwivedi <adwivedi@marvell.com>
> >
> > With the latest firmware, there are few changes for zuc and snow3g.
> >
> > 1. The iv_source is present in bitfield 7 of minor opcode. In the old firmware
> this
> > was present in bitfield 6.
> >
> > 2. Algorithm type is a 2 bit field in new firmware. In the old firmware it was
> > named as cipher type and it was a 1 bit field.
> >
> > Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
> > Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> > ---
From next time please delegate patch accordingly if the patch is intended for next-crypto
Applied to dpdk-next-crypto
Thanks.
@@ -303,8 +303,8 @@ struct cpt_ctx {
uint64_t hmac :1;
uint64_t zsk_flags :3;
uint64_t k_ecb :1;
- uint64_t snow3g :1;
- uint64_t rsvd :22;
+ uint64_t snow3g :2;
+ uint64_t rsvd :21;
/* Below fields are accessed by hardware */
union {
mc_fc_context_t fctx;
@@ -1467,7 +1467,8 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
- opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+
+ opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
(0 << 3) | (flags & 0x7));
if (flags == 0x1) {
@@ -1791,7 +1792,8 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
- opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
+
+ opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
(0 << 3) | (flags & 0x7));
/* consider iv len */