@@ -161,7 +161,8 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {
DEV_RX_OFFLOAD_JUMBO_FRAME | \
DEV_RX_OFFLOAD_KEEP_CRC | \
DEV_RX_OFFLOAD_TCP_LRO | \
- DEV_RX_OFFLOAD_RSS_HASH)
+ DEV_RX_OFFLOAD_RSS_HASH | \
+ DEV_RX_OFFLOAD_FLOW_MARK)
static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
@@ -199,7 +199,8 @@ int enic_get_vnic_config(struct enic *enic)
DEV_RX_OFFLOAD_IPV4_CKSUM |
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM |
- DEV_RX_OFFLOAD_RSS_HASH;
+ DEV_RX_OFFLOAD_RSS_HASH |
+ DEV_RX_OFFLOAD_FLOW_MARK;
enic->tx_offload_mask =
PKT_TX_IPV6 |
PKT_TX_IPV4 |
@@ -3512,7 +3512,8 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
DEV_RX_OFFLOAD_VLAN_EXTEND |
DEV_RX_OFFLOAD_VLAN_FILTER |
DEV_RX_OFFLOAD_JUMBO_FRAME |
- DEV_RX_OFFLOAD_RSS_HASH;
+ DEV_RX_OFFLOAD_RSS_HASH |
+ DEV_RX_OFFLOAD_FLOW_MARK;
dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
dev_info->tx_offload_capa =
@@ -518,7 +518,8 @@ iavf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
DEV_RX_OFFLOAD_SCATTER |
DEV_RX_OFFLOAD_JUMBO_FRAME |
DEV_RX_OFFLOAD_VLAN_FILTER |
- DEV_RX_OFFLOAD_RSS_HASH;
+ DEV_RX_OFFLOAD_RSS_HASH |
+ DEV_RX_OFFLOAD_FLOW_MARK;
dev_info->tx_offload_capa =
DEV_TX_OFFLOAD_VLAN_INSERT |
DEV_TX_OFFLOAD_QINQ_INSERT |
@@ -2146,7 +2146,8 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
DEV_RX_OFFLOAD_QINQ_STRIP |
DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
DEV_RX_OFFLOAD_VLAN_EXTEND |
- DEV_RX_OFFLOAD_RSS_HASH;
+ DEV_RX_OFFLOAD_RSS_HASH |
+ DEV_RX_OFFLOAD_FLOW_MARK;
dev_info->tx_offload_capa |=
DEV_TX_OFFLOAD_QINQ_INSERT |
DEV_TX_OFFLOAD_IPV4_CKSUM |
@@ -2873,7 +2873,8 @@ ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev)
DEV_RX_OFFLOAD_JUMBO_FRAME |
DEV_RX_OFFLOAD_VLAN_FILTER |
DEV_RX_OFFLOAD_SCATTER |
- DEV_RX_OFFLOAD_RSS_HASH;
+ DEV_RX_OFFLOAD_RSS_HASH |
+ DEV_RX_OFFLOAD_FLOW_MARK;
if (hw->mac.type == ixgbe_mac_82598EB)
offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
@@ -369,7 +369,8 @@ mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
DEV_RX_OFFLOAD_TIMESTAMP |
DEV_RX_OFFLOAD_JUMBO_FRAME |
- DEV_RX_OFFLOAD_RSS_HASH);
+ DEV_RX_OFFLOAD_RSS_HASH |
+ DEV_RX_OFFLOAD_FLOW_MARK);
if (config->hw_fcs_strip)
offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
@@ -141,7 +141,8 @@
DEV_RX_OFFLOAD_VLAN_FILTER | \
DEV_RX_OFFLOAD_QINQ_STRIP | \
DEV_RX_OFFLOAD_TIMESTAMP | \
- DEV_RX_OFFLOAD_RSS_HASH)
+ DEV_RX_OFFLOAD_RSS_HASH | \
+ DEV_RX_OFFLOAD_FLOW_MARK)
#define NIX_DEFAULT_RSS_CTX_GROUP 0
#define NIX_DEFAULT_RSS_MCAM_IDX -1
@@ -524,11 +524,8 @@ otx2_flow_destroy(struct rte_eth_dev *dev,
NIX_RX_ACT_MATCH_MASK;
if (match_id && match_id < OTX2_FLOW_ACTION_FLAG_DEFAULT) {
- if (rte_atomic32_read(&npc->mark_actions) == 0)
- return -EINVAL;
-
- /* Clear mark offload flag if there are no more mark actions */
- if (rte_atomic32_sub_return(&npc->mark_actions, 1) == 0) {
+ /* Clear mark offload flag if there is no more mark action */
+ if (hw->rx_offloads & DEV_RX_OFFLOAD_FLOW_MARK) {
hw->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
otx2_eth_set_rx_function(dev);
}
@@ -821,8 +818,6 @@ otx2_flow_init(struct otx2_eth_dev *hw)
return rc;
}
- rte_atomic32_init(&npc->mark_actions);
-
npc->mcam_entries = NPC_MCAM_TOT_ENTRIES >> npc->keyw[NPC_MCAM_RX];
/* Free, free_rev, live and live_rev entries */
bmap_sz = rte_bitmap_get_memory_footprint(npc->mcam_entries);
@@ -160,7 +160,6 @@ TAILQ_HEAD(otx2_flow_list, rte_flow);
/* Accessed from ethdev private - otx2_eth_dev */
struct otx2_npc_flow_info {
- rte_atomic32_t mark_actions;
uint32_t keyx_supp_nmask[NPC_MAX_INTF];/* nibble mask */
uint32_t keyx_len[NPC_MAX_INTF]; /* per intf key len in bits */
uint32_t datax_len[NPC_MAX_INTF]; /* per intf data len in bits */
@@ -761,7 +761,6 @@ otx2_flow_parse_actions(struct rte_eth_dev *dev,
struct rte_flow *flow)
{
struct otx2_eth_dev *hw = dev->data->dev_private;
- struct otx2_npc_flow_info *npc = &hw->npc_flow;
const struct rte_flow_action_count *act_count;
const struct rte_flow_action_mark *act_mark;
const struct rte_flow_action_queue *act_q;
@@ -795,13 +794,11 @@ otx2_flow_parse_actions(struct rte_eth_dev *dev,
}
mark = act_mark->id + 1;
req_act |= OTX2_FLOW_ACT_MARK;
- rte_atomic32_inc(&npc->mark_actions);
break;
case RTE_FLOW_ACTION_TYPE_FLAG:
mark = OTX2_FLOW_FLAG_VAL;
req_act |= OTX2_FLOW_ACT_FLAG;
- rte_atomic32_inc(&npc->mark_actions);
break;
case RTE_FLOW_ACTION_TYPE_COUNT:
@@ -979,7 +976,7 @@ otx2_flow_parse_actions(struct rte_eth_dev *dev,
if (mark)
flow->npc_action |= (uint64_t)mark << 40;
- if (rte_atomic32_read(&npc->mark_actions) == 1) {
+ if (hw->rx_offloads & DEV_RX_OFFLOAD_FLOW_MARK) {
hw->rx_offload_flags |=
NIX_RX_OFFLOAD_MARK_UPDATE_F;
otx2_eth_set_rx_function(dev);
@@ -716,7 +716,8 @@ struct sfc_dp_rx sfc_ef10_essb_rx = {
.features = SFC_DP_RX_FEAT_FLOW_FLAG |
SFC_DP_RX_FEAT_FLOW_MARK,
.dev_offload_capa = DEV_RX_OFFLOAD_CHECKSUM,
- .queue_offload_capa = DEV_RX_OFFLOAD_RSS_HASH,
+ .queue_offload_capa = DEV_RX_OFFLOAD_RSS_HASH |
+ DEV_RX_OFFLOAD_FLOW_MARK,
.get_dev_info = sfc_ef10_essb_rx_get_dev_info,
.pool_ops_supported = sfc_ef10_essb_rx_pool_ops_supported,
.qsize_up_rings = sfc_ef10_essb_rx_qsize_up_rings,