From patchwork Wed Oct 9 15:20:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Van Haaren, Harry" X-Patchwork-Id: 60822 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E47F61E950; Wed, 9 Oct 2019 17:20:50 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 7CFC21E91A for ; Wed, 9 Oct 2019 17:20:45 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Oct 2019 08:20:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,276,1566889200"; d="scan'208";a="218659802" Received: from silpixa00399779.ir.intel.com (HELO silpixa00399779.ger.corp.intel.com) ([10.237.222.100]) by fmsmga004.fm.intel.com with ESMTP; 09 Oct 2019 08:20:41 -0700 From: Harry van Haaren To: dev@dpdk.org Cc: qi.z.zhang@intel.com, mesut.a.ergin@intel.com, Harry van Haaren Date: Wed, 9 Oct 2019 16:20:05 +0100 Message-Id: <20191009152006.5768-3-harry.van.haaren@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191009152006.5768-1-harry.van.haaren@intel.com> References: <20191007090731.90073-1-harry.van.haaren@intel.com> <20191009152006.5768-1-harry.van.haaren@intel.com> Subject: [dpdk-dev] [PATCH v2 2/3] net/i40e: add flow mark capability to SSE vector routine X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds an implementation to the SSE vector implementation of RX routine and moves some common defines from a c file to the header file. I40e can have 16 and 32 byte descriptors, and the Flow Director ID data and indication-bit are in different locations for each size descriptor. The support is implemented in two seperate functions as they require vastly different operations. The 16B descriptor re-purposes the "filter-status" u32 field to indicate FDIR ID when the FLM bit is set. No extra loads are required, however we do have to store to mbuf->fdir.hi, which is not stored to in the RX path before this patch. The 32B descriptor requires loading the 2nd 16 bytes of each descriptor, to get the FLEXBH_STAT and FD Filter ID from qword3. The resulting data must also be stored to mbuf->fdir.hi, same as the 16B code path. Signed-off-by: Harry van Haaren --- v2; - Fix unused variable warning on 16B desc path - Fix RSS clearing for 16B descs. Note, this requires delaying the desc[] to mbuf shuffle, to clear the RSS data while in desc[] array. --- drivers/net/i40e/i40e_rxtx.c | 6 -- drivers/net/i40e/i40e_rxtx.h | 7 ++ drivers/net/i40e/i40e_rxtx_vec_sse.c | 154 +++++++++++++++++++++++++-- 3 files changed, 152 insertions(+), 15 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 692c3bab4..5fffb34ee 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -172,12 +172,6 @@ i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword) } #endif -#define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03 -#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01 -#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02 -#define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03 -#define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01 - static inline uint64_t i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb) { diff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h index 1028e8b68..2106bb355 100644 --- a/drivers/net/i40e/i40e_rxtx.h +++ b/drivers/net/i40e/i40e_rxtx.h @@ -32,6 +32,13 @@ #define I40E_TX_MIN_PKT_LEN 17 +/* Shared FDIR masks between scalar / vector drivers */ +#define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03 +#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01 +#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02 +#define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03 +#define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01 + #undef container_of #define container_of(ptr, type, member) ({ \ typeof(((type *)0)->member)(*__mptr) = (ptr); \ diff --git a/drivers/net/i40e/i40e_rxtx_vec_sse.c b/drivers/net/i40e/i40e_rxtx_vec_sse.c index 1fc66b781..6ab0bb0d3 100644 --- a/drivers/net/i40e/i40e_rxtx_vec_sse.c +++ b/drivers/net/i40e/i40e_rxtx_vec_sse.c @@ -89,9 +89,131 @@ i40e_rxq_rearm(struct i40e_rx_queue *rxq) I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id); } +#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC +/* SSE version of FDIR mark extraction for 4 32B descriptors at a time */ +static inline __m128i +descs_to_fdir_32b(volatile union i40e_rx_desc *rxdp, struct rte_mbuf **rx_pkt) +{ + /* 32B descriptors: Load 2nd half of descriptors for FDIR ID data */ + __m128i desc0_qw23, desc1_qw23, desc2_qw23, desc3_qw23; + desc0_qw23 = _mm_loadu_si128((__m128i *)&(rxdp + 0)->wb.qword2); + desc1_qw23 = _mm_loadu_si128((__m128i *)&(rxdp + 1)->wb.qword2); + desc2_qw23 = _mm_loadu_si128((__m128i *)&(rxdp + 2)->wb.qword2); + desc3_qw23 = _mm_loadu_si128((__m128i *)&(rxdp + 3)->wb.qword2); + + /* FDIR ID data: move last u32 of each desc to 4 u32 lanes */ + __m128i v_unpack_01, v_unpack_23; + v_unpack_01 = _mm_unpackhi_epi32(desc0_qw23, desc1_qw23); + v_unpack_23 = _mm_unpackhi_epi32(desc2_qw23, desc3_qw23); + __m128i v_fdir_ids = _mm_unpackhi_epi64(v_unpack_01, v_unpack_23); + + /* Extended Status: extract from each lower 32 bits, to u32 lanes */ + v_unpack_01 = _mm_unpacklo_epi32(desc0_qw23, desc1_qw23); + v_unpack_23 = _mm_unpacklo_epi32(desc2_qw23, desc3_qw23); + __m128i v_flt_status = _mm_unpacklo_epi64(v_unpack_01, v_unpack_23); + + /* Shift u32 left and right to "mask away" bits not required. + * Data required is 4:5 (zero based), so left shift by 26 (32-6) + * and then right shift by 30 (32 - 2 bits required). + */ + v_flt_status = _mm_slli_epi32(v_flt_status, 26); + v_flt_status = _mm_srli_epi32(v_flt_status, 30); + + /* Generate constant 1 in all u32 lanes and compare */ + RTE_BUILD_BUG_ON(I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID != 1); + __m128i v_zeros = _mm_setzero_si128(); + __m128i v_ffff = _mm_cmpeq_epi32(v_zeros, v_zeros); + __m128i v_u32_one = _mm_srli_epi32(v_ffff, 31); + + /* per desc mask, bits set if FDIR ID is valid */ + __m128i v_fd_id_mask = _mm_cmpeq_epi32(v_flt_status, v_u32_one); + + /* Mask ID data to zero if the FD_ID bit not set in desc */ + v_fdir_ids = _mm_and_si128(v_fdir_ids, v_fd_id_mask); + + /* Extract and store as u32. No advantage to combining into SSE + * stores, there are no surrounding stores to around fdir.hi + */ + rx_pkt[0]->hash.fdir.hi = _mm_extract_epi32(v_fdir_ids, 0); + rx_pkt[1]->hash.fdir.hi = _mm_extract_epi32(v_fdir_ids, 1); + rx_pkt[2]->hash.fdir.hi = _mm_extract_epi32(v_fdir_ids, 2); + rx_pkt[3]->hash.fdir.hi = _mm_extract_epi32(v_fdir_ids, 3); + + /* convert fdir_id_mask into a single bit, then shift as required for + * correct location in the mbuf->olflags + */ + const uint32_t FDIR_ID_BIT_SHIFT = 13; + RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << FDIR_ID_BIT_SHIFT)); + v_fd_id_mask = _mm_srli_epi32(v_fd_id_mask, 31); + v_fd_id_mask = _mm_slli_epi32(v_fd_id_mask, FDIR_ID_BIT_SHIFT); + + /* The returned value must be combined into each mbuf. This is already + * being done for RSS and VLAN mbuf olflags, so return bits to OR in. + */ + return v_fd_id_mask; +} + +#else /* 32 or 16B FDIR ID handling */ + +/* Handle 16B descriptor FDIR ID flag setting based on FLM. See scalar driver + * for scalar implementation of the same functionality. + */ +static inline __m128i +descs_to_fdir_16b(__m128i fltstat, __m128i descs[4], struct rte_mbuf **rx_pkt) +{ + /* unpack filter-status data from descriptors */ + __m128i v_tmp_01 = _mm_unpacklo_epi32(descs[0], descs[1]); + __m128i v_tmp_23 = _mm_unpacklo_epi32(descs[2], descs[3]); + __m128i v_fdir_ids = _mm_unpackhi_epi64(v_tmp_01, v_tmp_23); + + /* Generate one bit in each u32 lane */ + __m128i v_zeros = _mm_setzero_si128(); + __m128i v_ffff = _mm_cmpeq_epi32(v_zeros, v_zeros); + __m128i v_111_mask = _mm_srli_epi32(v_ffff, 29); + __m128i v_11_mask = _mm_srli_epi32(v_ffff, 30); + + /* Top lane ones mask for FDIR isolation */ + __m128i v_desc_fdir_mask = _mm_insert_epi32(v_zeros, UINT32_MAX, 1); + + /* Compare and mask away FDIR ID data if bit not set */ + __m128i v_u32_bits = _mm_and_si128(v_111_mask, fltstat); + __m128i v_fdir_id_mask = _mm_cmpeq_epi32(v_u32_bits, v_11_mask); + v_fdir_ids = _mm_and_si128(v_fdir_id_mask, v_fdir_ids); + + /* Store data to fdir.hi in mbuf */ + rx_pkt[0]->hash.fdir.hi = _mm_extract_epi32(v_fdir_ids, 0); + rx_pkt[1]->hash.fdir.hi = _mm_extract_epi32(v_fdir_ids, 1); + rx_pkt[2]->hash.fdir.hi = _mm_extract_epi32(v_fdir_ids, 2); + rx_pkt[3]->hash.fdir.hi = _mm_extract_epi32(v_fdir_ids, 3); + + /* Move fdir_id_mask to correct lane, blend RSS to zero on hits */ + __m128i v_desc3_shift = _mm_alignr_epi8(v_zeros, v_fdir_id_mask, 8); + __m128i v_desc3_mask = _mm_and_si128(v_desc_fdir_mask, v_desc3_shift); + descs[3] = _mm_blendv_epi8(descs[3], _mm_setzero_si128(), v_desc3_mask); + + __m128i v_desc2_shift = _mm_alignr_epi8(v_zeros, v_fdir_id_mask, 4); + __m128i v_desc2_mask = _mm_and_si128(v_desc_fdir_mask, v_desc2_shift); + descs[2] = _mm_blendv_epi8(descs[2], _mm_setzero_si128(), v_desc2_mask); + + __m128i v_desc1_shift = v_fdir_id_mask; + __m128i v_desc1_mask = _mm_and_si128(v_desc_fdir_mask, v_desc1_shift); + descs[1] = _mm_blendv_epi8(descs[1], _mm_setzero_si128(), v_desc1_mask); + + __m128i v_desc0_shift = _mm_alignr_epi8(v_fdir_id_mask, v_zeros, 12); + __m128i v_desc0_mask = _mm_and_si128(v_desc_fdir_mask, v_desc0_shift); + descs[0] = _mm_blendv_epi8(descs[0], _mm_setzero_si128(), v_desc0_mask); + + /* Shift to 1 or 0 bit per u32 lane, then to PKT_RX_FDIR_ID offset */ + const uint32_t FDIR_ID_BIT_SHIFT = 13; + RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << FDIR_ID_BIT_SHIFT)); + __m128i v_mask_one_bit = _mm_srli_epi32(v_fdir_id_mask, 31); + return _mm_slli_epi32(v_mask_one_bit, FDIR_ID_BIT_SHIFT); +} +#endif + static inline void -desc_to_olflags_v(struct i40e_rx_queue *rxq, __m128i descs[4], - struct rte_mbuf **rx_pkts) +desc_to_olflags_v(struct i40e_rx_queue *rxq, volatile union i40e_rx_desc *rxdp, + __m128i descs[4], struct rte_mbuf **rx_pkts) { const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer); __m128i rearm0, rearm1, rearm2, rearm3; @@ -143,6 +265,7 @@ desc_to_olflags_v(struct i40e_rx_queue *rxq, __m128i descs[4], PKT_RX_IP_CKSUM_BAD >> 1, (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1); + /* Unpack "status" from quadword 1, bits 0:32 */ vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]); vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]); vlan0 = _mm_unpacklo_epi64(vlan0, vlan1); @@ -150,8 +273,8 @@ desc_to_olflags_v(struct i40e_rx_queue *rxq, __m128i descs[4], vlan1 = _mm_and_si128(vlan0, rss_vlan_msk); vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1); - rss = _mm_srli_epi32(vlan1, 11); - rss = _mm_shuffle_epi8(rss_flags, rss); + const __m128i desc_fltstat = _mm_srli_epi32(vlan1, 11); + rss = _mm_shuffle_epi8(rss_flags, desc_fltstat); l3_l4e = _mm_srli_epi32(vlan1, 22); l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e); @@ -163,6 +286,19 @@ desc_to_olflags_v(struct i40e_rx_queue *rxq, __m128i descs[4], vlan0 = _mm_or_si128(vlan0, rss); vlan0 = _mm_or_si128(vlan0, l3_l4e); + /* Extract FDIR ID only if FDIR is enabled to avoid useless work */ + if (rxq->fdir_enabled) { +#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC + __m128i v_fdir_ol_flags = descs_to_fdir_32b(rxdp, rx_pkts); +#else + (void)rxdp; /* rxdp not required for 16B desc mode */ + __m128i v_fdir_ol_flags = descs_to_fdir_16b(desc_fltstat, + descs, rx_pkts); +#endif + /* OR in ol_flag bits after descriptor speicific extraction */ + vlan0 = _mm_or_si128(vlan0, v_fdir_ol_flags); + } + /* * At this point, we have the 4 sets of flags in the low 16-bits * of each 32-bit value in vlan0. @@ -368,16 +504,16 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, descs[3] = _mm_blend_epi16(descs[3], len3, 0x80); descs[2] = _mm_blend_epi16(descs[2], len2, 0x80); - /* D.1 pkt 3,4 convert format from desc to pktmbuf */ - pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk); - pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk); - /* C.1 4=>2 filter staterr info only */ sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]); /* C.1 4=>2 filter staterr info only */ sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]); - desc_to_olflags_v(rxq, descs, &rx_pkts[pos]); + desc_to_olflags_v(rxq, rxdp, descs, &rx_pkts[pos]); + + /* D.1 pkt 3,4 convert format from desc to pktmbuf */ + pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk); + pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk); /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */ pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);