From patchwork Thu Oct 10 01:41:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 60843 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EDF311E8E3; Thu, 10 Oct 2019 03:42:26 +0200 (CEST) Received: from rnd-relay.smtp.broadcom.com (rnd-relay.smtp.broadcom.com [192.19.229.170]) by dpdk.org (Postfix) with ESMTP id 011D91E4DF; Thu, 10 Oct 2019 03:42:01 +0200 (CEST) Received: from mail-irv-17.broadcom.com (mail-irv-17.lvn.broadcom.net [10.75.242.48]) by rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id 77AEE30C13A; Wed, 9 Oct 2019 18:40:26 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com 77AEE30C13A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1570671626; bh=nvXQTp/yO1loPFRpmjnZHWkywTWY0kbC3mtdZ5Ly0Gw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VWIhkVrmDAjWiHTfGn9dFZ1FT8+ApYKC3RK2NYpFhm7cqvsoO8nAEc0eMLIXp5LZt Iv/wxDxniKSd1mhMOfA0WJ7XtV4+cFRjXN0NywADbbsqQS4W8MrXJo3Y59iK98Le+5 BNQLpNYRUDxXJobhjkyvYZsyXWkwuJzrk3yqivxU= Received: from localhost.localdomain (unknown [10.230.30.225]) by mail-irv-17.broadcom.com (Postfix) with ESMTP id C136E140069; Wed, 9 Oct 2019 18:41:58 -0700 (PDT) From: Ajit Khaparde To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Rahul Gupta , stable@dpdk.org Date: Wed, 9 Oct 2019 18:41:49 -0700 Message-Id: <20191010014153.64908-9-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.20.1 (Apple Git-117) In-Reply-To: <20191010014153.64908-1-ajit.khaparde@broadcom.com> References: <167a2652-7ad6-e02a-8a02-01f828bcba8c@intel.com> <20191010014153.64908-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 08/12] net/bnxt: change msix vector to queue mapping X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Rahul Gupta DPDK PCIe-VFIO framework configures base MSIX vector for interrupts which is supported by other h/w. In case of bnxt, base MSIX vector starts with the RX completion queue 0. To comply with the DPDK framework We need to increase the map index by 1 so that RXTX completion queues events can be delivered to appropriate event listeners by kernel VFIO. Fixes: bd0a14c99f65 ("net/bnxt: use dedicated CPR for async events") Cc: stable@dpdk.org Signed-off-by: Rahul Gupta Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt.h | 3 +++ drivers/net/bnxt/bnxt_irq.h | 3 --- drivers/net/bnxt/bnxt_ring.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 5020cd3415..080365804c 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -58,6 +58,9 @@ #define BNXT_NUM_ASYNC_CPR(bp) 1 #endif +#define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET +#define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET + /* Chimp Communication Channel */ #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 diff --git a/drivers/net/bnxt/bnxt_irq.h b/drivers/net/bnxt/bnxt_irq.h index 1b56e08068..ad8a1df9ca 100644 --- a/drivers/net/bnxt/bnxt_irq.h +++ b/drivers/net/bnxt/bnxt_irq.h @@ -6,9 +6,6 @@ #ifndef _BNXT_IRQ_H_ #define _BNXT_IRQ_H_ -#define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET -#define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET - struct bnxt_irq { rte_intr_callback_fn handler; unsigned int vector; diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c index 886029c575..19af727635 100644 --- a/drivers/net/bnxt/bnxt_ring.c +++ b/drivers/net/bnxt/bnxt_ring.c @@ -406,7 +406,7 @@ static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index, { struct bnxt_ring *cp_ring = cpr->cp_ring_struct; uint32_t nq_ring_id = HWRM_NA_SIGNATURE; - int cp_ring_index = queue_index + BNXT_NUM_ASYNC_CPR(bp); + int cp_ring_index = queue_index + BNXT_RX_VEC_START; struct bnxt_cp_ring_info *nqr = bp->rxtx_nq_ring; uint8_t ring_type; int rc = 0;