[v8,09/18] raw/ifpga/base: update SEU register definition
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Message ID 1570782089-182978-10-git-send-email-andy.pei@intel.com
State Superseded
Delegated to: xiaolong ye
Headers show
Series
  • add PCIe AER disable and IRQ support for ipn3ke
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Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail Compilation issues

Commit Message

Pei, Andy Oct. 11, 2019, 8:21 a.m. UTC
From: Tianfei zhang <tianfei.zhang@intel.com>

Update the SEU registser definition.

Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
Signed-off-by: Andy Pei <andy.pei@intel.com>
---
 drivers/raw/ifpga/base/ifpga_defines.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Patch
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diff --git a/drivers/raw/ifpga/base/ifpga_defines.h b/drivers/raw/ifpga/base/ifpga_defines.h
index b450cb1..8993cc6 100644
--- a/drivers/raw/ifpga/base/ifpga_defines.h
+++ b/drivers/raw/ifpga/base/ifpga_defines.h
@@ -1122,7 +1122,9 @@  struct feature_fme_ras_catfaterror {
 			u8  therm_catast_err:1;
 			/* Injected Catastrophic Error */
 			u8  injected_catast_err:1;
-			u64 rsvd:52;
+			/* SEU error on BMC */
+			u8  bmc_seu_catast_err:1;
+			u64 rsvd:51;
 		};
 	};
 };