[1/2] event/dpaa: fix number of supported atomic flows
diff mbox series

Message ID 20191011134757.3359-1-nipun.gupta@nxp.com
State Accepted
Delegated to: Jerin Jacob
Headers show
Series
  • [1/2] event/dpaa: fix number of supported atomic flows
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Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail Compilation issues

Commit Message

Nipun Gupta Oct. 11, 2019, 1:47 p.m. UTC
The number of atomic flows supported was not returned correctly for
DPAA driver. This patch fixes the same.

Fixes: b08dc6430abd ("event/dpaa: add queue config get/set")
Cc: stable@dpdk.org

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
---
 drivers/event/dpaa/dpaa_eventdev.c | 1 +
 drivers/event/dpaa/dpaa_eventdev.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

Comments

Hemant Agrawal Oct. 16, 2019, 6:40 a.m. UTC | #1
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Jerin Jacob Oct. 16, 2019, 7:58 a.m. UTC | #2
On Wed, Oct 16, 2019 at 12:11 PM Hemant Agrawal <hemant.agrawal@nxp.com> wrote:
>
> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
>

Series applied to dpdk-next-eventdev/master. Thanks.

Patch
diff mbox series

diff --git a/drivers/event/dpaa/dpaa_eventdev.c b/drivers/event/dpaa/dpaa_eventdev.c
index d02b8694e..570983251 100644
--- a/drivers/event/dpaa/dpaa_eventdev.c
+++ b/drivers/event/dpaa/dpaa_eventdev.c
@@ -471,6 +471,7 @@  dpaa_event_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
 	RTE_SET_USED(queue_id);
 
 	memset(queue_conf, 0, sizeof(struct rte_event_queue_conf));
+	queue_conf->nb_atomic_flows = DPAA_EVENT_QUEUE_ATOMIC_FLOWS;
 	queue_conf->schedule_type = RTE_SCHED_TYPE_PARALLEL;
 	queue_conf->priority = RTE_EVENT_DEV_PRIORITY_HIGHEST;
 }
diff --git a/drivers/event/dpaa/dpaa_eventdev.h b/drivers/event/dpaa/dpaa_eventdev.h
index b8f247c61..5ce15a3db 100644
--- a/drivers/event/dpaa/dpaa_eventdev.h
+++ b/drivers/event/dpaa/dpaa_eventdev.h
@@ -32,7 +32,7 @@  do {						\
 	RTE_EVENT_DEV_CAP_BURST_MODE;		\
 } while (0)
 
-#define DPAA_EVENT_QUEUE_ATOMIC_FLOWS	0
+#define DPAA_EVENT_QUEUE_ATOMIC_FLOWS		2048
 #define DPAA_EVENT_QUEUE_ORDER_SEQUENCES	2048
 
 #define RTE_EVENT_ETH_RX_ADAPTER_DPAA_CAP \