From patchwork Sat Oct 12 00:27:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alfredo Cardigliano X-Patchwork-Id: 61006 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 496CE1EBC0; Sat, 12 Oct 2019 02:27:48 +0200 (CEST) Received: from devele.ntop.org (net-93-145-196-230.cust.vodafonedsl.it [93.145.196.230]) by dpdk.org (Postfix) with ESMTP id B10411EBBF for ; Sat, 12 Oct 2019 02:27:47 +0200 (CEST) Received: from [192.168.2.134] (localhost6.localdomain6 [IPv6:::1]) by devele.ntop.org (Postfix) with ESMTP id 8C3896C003C for ; Sat, 12 Oct 2019 02:27:47 +0200 (CEST) From: Alfredo Cardigliano To: dev@dpdk.org Date: Sat, 12 Oct 2019 02:27:47 +0200 Message-ID: <157084006752.11524.15673323462243958303.stgit@devele> In-Reply-To: <157083994018.11524.11276616720287263690.stgit@devele> References: <157083994018.11524.11276616720287263690.stgit@devele> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 16/17] net/ionic: add TX checksum support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for TX checksumming. Signed-off-by: Alfredo Cardigliano Reviewed-by: Shannon Nelson --- drivers/net/ionic/ionic_ethdev.c | 5 ++ drivers/net/ionic/ionic_lif.c | 1 drivers/net/ionic/ionic_lif.h | 1 drivers/net/ionic/ionic_rxtx.c | 86 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c index 1300774a9..720598dbd 100644 --- a/drivers/net/ionic/ionic_ethdev.c +++ b/drivers/net/ionic/ionic_ethdev.c @@ -413,7 +413,12 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev, 0; dev_info->tx_queue_offload_capa = + DEV_TX_OFFLOAD_IPV4_CKSUM | + DEV_TX_OFFLOAD_UDP_CKSUM | + DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_VLAN_INSERT | + DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | + DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 0; /* diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index e2cefbaf6..6f1cbf8fb 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -1506,6 +1506,7 @@ ionic_lif_init(struct ionic_lif *lif) | IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_TX_SG | IONIC_ETH_HW_RX_SG + | IONIC_ETH_HW_TX_CSUM | IONIC_ETH_HW_RX_CSUM | IONIC_ETH_HW_TSO | IONIC_ETH_HW_TSO_IPV6 diff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h index aa2f849c0..8feaad7e3 100644 --- a/drivers/net/ionic/ionic_lif.h +++ b/drivers/net/ionic/ionic_lif.h @@ -32,6 +32,7 @@ struct ionic_tx_stats { uint64_t bytes; uint64_t drop; uint64_t stop; + uint64_t no_csum; uint64_t tso; uint64_t frags; }; diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index 1a7313cc3..09600c953 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -231,16 +231,59 @@ ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) return 0; } +static void +ionic_tx_tcp_pseudo_csum(struct rte_mbuf *txm) +{ + struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *); + char *l3_hdr = ((char *)eth_hdr) + txm->l2_len; + struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *) + (l3_hdr + txm->l3_len); + + if (txm->ol_flags & PKT_TX_IP_CKSUM) { + struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr; + ipv4_hdr->hdr_checksum = 0; + tcp_hdr->cksum = 0; + tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr); + } else { + struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr; + tcp_hdr->cksum = 0; + tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr); + } +} + +static void +ionic_tx_tcp_inner_pseudo_csum(struct rte_mbuf *txm) +{ + struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *); + char *l3_hdr = ((char *)eth_hdr) + txm->outer_l2_len + + txm->outer_l3_len + txm->l2_len; + struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *) + (l3_hdr + txm->l3_len); + + if (txm->ol_flags & PKT_TX_IPV4) { + struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr; + ipv4_hdr->hdr_checksum = 0; + tcp_hdr->cksum = 0; + tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr); + } else { + struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr; + tcp_hdr->cksum = 0; + tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr); + } +} + static void ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc, struct rte_mbuf *txm, rte_iova_t addr, uint8_t nsge, uint16_t len, uint32_t hdrlen, uint32_t mss, + bool encap, uint16_t vlan_tci, bool has_vlan, bool start, bool done) { uint8_t flags = 0; flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; + flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0; flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0; @@ -285,10 +328,29 @@ ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm, uint64_t offloads, uint32_t len; uint32_t offset = 0; bool start, done; + bool encap; bool has_vlan = !!(txm->ol_flags & PKT_TX_VLAN_PKT); uint16_t vlan_tci = txm->vlan_tci; + uint64_t ol_flags = txm->ol_flags; + + encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) || + (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) && + ((ol_flags & PKT_TX_OUTER_IPV4) || + (ol_flags & PKT_TX_OUTER_IPV6)); + + /* Preload inner-most TCP csum field with IP pseudo hdr + * calculated with IP length set to zero. HW will later + * add in length to each TCP segment resulting from the TSO. + */ - hdrlen = txm->l2_len + txm->l3_len; + if (encap) { + ionic_tx_tcp_inner_pseudo_csum(txm); + hdrlen = txm->outer_l2_len + txm->outer_l3_len + + txm->l2_len + txm->l3_len + txm->l4_len; + } else { + ionic_tx_tcp_pseudo_csum(txm); + hdrlen = txm->l2_len + txm->l3_len + txm->l4_len; + } seglen = hdrlen + mss; left = txm->data_len; @@ -312,6 +374,7 @@ ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm, uint64_t offloads, ionic_tx_tso_post(q, desc, txm, desc_addr, desc_nsge, desc_len, hdrlen, mss, + encap, vlan_tci, has_vlan, start, done && not_xmit_more); desc = ionic_tx_tso_next(q, &elem); @@ -350,6 +413,7 @@ ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm, uint64_t offloads, ionic_tx_tso_post(q, desc, txm_seg, desc_addr, desc_nsge, desc_len, hdrlen, mss, + encap, vlan_tci, has_vlan, start, done && not_xmit_more); desc = ionic_tx_tso_next(q, &elem); @@ -375,15 +439,34 @@ ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm, uint64_t offloads, struct ionic_txq_sg_elem *elem = sg_desc->elems; struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q); struct rte_mbuf *txm_seg; + bool encap; bool has_vlan; uint64_t ol_flags = txm->ol_flags; uint64_t addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(txm)); uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE; uint8_t flags = 0; + if ((ol_flags & PKT_TX_IP_CKSUM) && + (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) { + opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; + flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3; + if (((ol_flags & PKT_TX_TCP_CKSUM) && + (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) || + ((ol_flags & PKT_TX_UDP_CKSUM) && + (offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) + flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4; + } else { + stats->no_csum++; + } + has_vlan = (ol_flags & PKT_TX_VLAN_PKT); + encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) || + (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) && + ((ol_flags & PKT_TX_OUTER_IPV4) || + (ol_flags & PKT_TX_OUTER_IPV6)); flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; + flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; desc->cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr); desc->len = txm->data_len; @@ -468,6 +551,7 @@ ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, PKT_TX_IPV4 | \ PKT_TX_IPV6 | \ PKT_TX_VLAN | \ + PKT_TX_IP_CKSUM | \ PKT_TX_TCP_SEG | \ PKT_TX_L4_MASK)