[v4] bus/pci: align next mapping address on page boundary

Message ID 78A93308629D474AA53B84C5879E84D24B10A29B@DGGEMM533-MBX.china.huawei.com (mailing list archive)
State Accepted, archived
Delegated to: David Marchand
Headers
Series [v4] bus/pci: align next mapping address on page boundary |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-compilation success Compile Testing PASS
ci/travis-robot success Travis build: passed
ci/Intel-compilation success Compilation OK
ci/iol-mellanox-Performance success Performance Testing PASS

Commit Message

Wangyu (Eric) Nov. 13, 2019, 7:17 a.m. UTC
  Currently, the next address picked by PCI mapping infrastructure
may be page-unaligned due to BAR length being smaller than page size.
This leads to a situation where the requested map address is invalid,
resulting in mmap() call returning an arbitrary address,
which will later interfere with device BAR mapping in secondary processes.

Fix it by always aligning the next requested address on page boundary.

Signed-off-by: Xiaofeng Deng <dengxiaofeng@huawei.com>
Signed-off-by: Wangyu (Eric) <seven.wangyu@huawei.com>
Acked-by: Wei Hu <xavier.huwei@huawei.com>
Acked-by: Min Hu <humin29@huawei.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>

Fixes: c752998b5e2e ("pci: introduce library and driver")
Cc: stable@dpdk.org
---
 drivers/bus/pci/linux/pci_uio.c  | 2 ++  drivers/bus/pci/linux/pci_vfio.c | 3 +++
 2 files changed, 5 insertions(+)

--
1.8.3.1
  

Comments

David Marchand Nov. 14, 2019, 1:14 p.m. UTC | #1
On Wed, Nov 13, 2019 at 8:17 AM Wangyu (Eric) <seven.wangyu@huawei.com> wrote:
>
> Currently, the next address picked by PCI mapping infrastructure
> may be page-unaligned due to BAR length being smaller than page size.
> This leads to a situation where the requested map address is invalid,
> resulting in mmap() call returning an arbitrary address,
> which will later interfere with device BAR mapping in secondary processes.
>
> Fix it by always aligning the next requested address on page boundary.
>
> Signed-off-by: Xiaofeng Deng <dengxiaofeng@huawei.com>
> Signed-off-by: Wangyu (Eric) <seven.wangyu@huawei.com>
> Acked-by: Wei Hu <xavier.huwei@huawei.com>
> Acked-by: Min Hu <humin29@huawei.com>
> Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
> Acked-by: Gavin Hu (Arm Technology China) <Gavin.Hu@arm.com>
>
> Fixes: c752998b5e2e ("pci: introduce library and driver")
> Cc: stable@dpdk.org

Cc'd stable.

Applied, thanks.



--
David Marchand
  

Patch

diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c index 6dca05a..097dc19 100644
--- a/drivers/bus/pci/linux/pci_uio.c
+++ b/drivers/bus/pci/linux/pci_uio.c
@@ -351,6 +351,8 @@ 
 	pci_map_addr = RTE_PTR_ADD(mapaddr,
 			(size_t)dev->mem_resource[res_idx].len);
 
+	pci_map_addr = RTE_PTR_ALIGN(pci_map_addr, sysconf(_SC_PAGE_SIZE));
+
 	maps[map_idx].phaddr = dev->mem_resource[res_idx].phys_addr;
 	maps[map_idx].size = dev->mem_resource[res_idx].len;
 	maps[map_idx].addr = mapaddr;
diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c
index b8faa23..64cd84a 100644
--- a/drivers/bus/pci/linux/pci_vfio.c
+++ b/drivers/bus/pci/linux/pci_vfio.c
@@ -750,6 +750,9 @@ 
 		bar_addr = pci_map_addr;
 		pci_map_addr = RTE_PTR_ADD(bar_addr, (size_t) reg->size);
 
+		pci_map_addr = RTE_PTR_ALIGN(pci_map_addr,
+					sysconf(_SC_PAGE_SIZE));
+
 		maps[i].addr = bar_addr;
 		maps[i].offset = reg->offset;
 		maps[i].size = reg->size;