From patchwork Thu Dec 5 12:38:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 63585 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2D04AA04F2; Thu, 5 Dec 2019 13:36:16 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 70EE81BF98; Thu, 5 Dec 2019 13:35:53 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 4D8901BF86 for ; Thu, 5 Dec 2019 13:35:46 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Dec 2019 04:35:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,281,1571727600"; d="scan'208";a="209122730" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by fmsmga008.fm.intel.com with ESMTP; 05 Dec 2019 04:35:44 -0800 From: Qi Zhang To: qiming.yang@intel.com Cc: xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang , Bruce Allan , Paul M Stillwell Jr Date: Thu, 5 Dec 2019 20:38:38 +0800 Message-Id: <20191205123847.39579-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191205123847.39579-1-qi.z.zhang@intel.com> References: <20191205123847.39579-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 03/12] net/ice/base: do not wait for PE unit to load X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When RDMA is not enabled, when checking for completion of a CORER or GLOBR do not wait for the PE unit to be loaded (indicated by GLNVM_ULD register's PE_DONE bit being set) since that does not happen and will cause issues such as failing to initialize the device. Signed-off-by: Bruce Allan Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 4ba3ab202..bb763913a 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -325,6 +325,7 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, if (!pi) return ICE_ERR_PARAM; hw = pi->hw; + li_old = &pi->phy.link_info_old; hw_media_type = &pi->phy.media_type; li = &pi->phy.link_info; @@ -645,7 +646,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw) ice_clear_pxe_mode(hw); - status = ice_get_caps(hw); if (status) goto err_unroll_cqinit; @@ -666,7 +666,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw) goto err_unroll_alloc; hw->evb_veb = true; - /* Query the allocated resources for Tx scheduler */ status = ice_sched_query_res_alloc(hw); if (status) { @@ -785,7 +784,7 @@ void ice_deinit_hw(struct ice_hw *hw) */ enum ice_status ice_check_reset(struct ice_hw *hw) { - u32 cnt, reg = 0, grst_delay; + u32 cnt, reg = 0, grst_delay, uld_mask; /* Poll for Device Active state in case a recent CORER, GLOBR, * or EMPR has occurred. The grst delay value is in 100ms units. @@ -807,13 +806,20 @@ enum ice_status ice_check_reset(struct ice_hw *hw) return ICE_ERR_RESET_FAILED; } -#define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ - GLNVM_ULD_GLOBR_DONE_M) +#define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ + GLNVM_ULD_PCIER_DONE_1_M |\ + GLNVM_ULD_CORER_DONE_M |\ + GLNVM_ULD_GLOBR_DONE_M |\ + GLNVM_ULD_POR_DONE_M |\ + GLNVM_ULD_POR_DONE_1_M |\ + GLNVM_ULD_PCIER_DONE_2_M) + + uld_mask = ICE_RESET_DONE_MASK; /* Device is Active; check Global Reset processes are done */ for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { - reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; - if (reg == ICE_RESET_DONE_MASK) { + reg = rd32(hw, GLNVM_ULD) & uld_mask; + if (reg == uld_mask) { ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); break;