[03/15] crypto/octeontx2: configure for inline IPsec
diff mbox series

Message ID 1575806094-28391-4-git-send-email-anoobj@marvell.com
State Superseded, archived
Delegated to: akhil goyal
Headers show
Series
  • add OCTEONTX2 inline IPsec support
Related show

Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/checkpatch warning coding style issues

Commit Message

Anoob Joseph Dec. 8, 2019, 11:54 a.m. UTC
From: Tejasree Kondoj <ktejasree@marvell.com>

For enabling outbound inline IPsec, a CPT queue needs to be tied
to a NIX PF_FUNC. Distribute CPT queues fairly among all availble
otx2 eth ports.

For inbound, one CPT LF will be assigned and initialized by kernel.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
---
 drivers/crypto/octeontx2/Makefile              |  3 +-
 drivers/crypto/octeontx2/meson.build           |  2 +
 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 53 ++++++++++++++++++++++++++
 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h |  7 ++++
 drivers/crypto/octeontx2/otx2_cryptodev_ops.c  | 38 ++++++++++++++++++
 5 files changed, 102 insertions(+), 1 deletion(-)

Comments

Jerin Jacob Dec. 9, 2019, 7:46 a.m. UTC | #1
On Sun, Dec 8, 2019 at 5:26 PM Anoob Joseph <anoobj@marvell.com> wrote:
>
> From: Tejasree Kondoj <ktejasree@marvell.com>
>
> For enabling outbound inline IPsec, a CPT queue needs to be tied
> to a NIX PF_FUNC. Distribute CPT queues fairly among all availble
> otx2 eth ports.
>
> For inbound, one CPT LF will be assigned and initialized by kernel.
>
> Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
> Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> Signed-off-by: Archana Muniganti <marchana@marvell.com>
> Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>

>
> +static int
> +otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
> +{
> +       static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
> +       uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
> +       int i, ret;
> +
> +       for (i = 0; i < nb_ethport; i++) {
> +               port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
> +               if (otx2_is_ethdev(&rte_eth_devices[port_id]))
> +                       break;
> +       }
> +
> +       if (i >= nb_ethport)
> +               return 0;
> +
> +       ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
> +       if (ret)
> +               return ret;
> +
> +       return 0;

Last five lines can be replaced with "return
otx2_cpt_qp_ethdev_bind(dev, qp, port_id)"

Across the patch series, the above pattern is common, Please fix in
all relevant instances.
Anoob Joseph Dec. 9, 2019, 7:52 a.m. UTC | #2
Hi Jerin,

Please see inline.

Thanks,
Anoob

> -----Original Message-----
> From: Jerin Jacob <jerinjacobk@gmail.com>
> Sent: Monday, December 9, 2019 1:17 PM
> To: Anoob Joseph <anoobj@marvell.com>
> Cc: Akhil Goyal <akhil.goyal@nxp.com>; Declan Doherty
> <declan.doherty@intel.com>; Thomas Monjalon <thomas@monjalon.net>;
> Tejasree Kondoj <ktejasree@marvell.com>; Jerin Jacob Kollanukkaran
> <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> <pathreya@marvell.com>; Kiran Kumar Kokkilagadda
> <kirankumark@marvell.com>; Nithin Kumar Dabilpuram
> <ndabilpuram@marvell.com>; Pavan Nikhilesh Bhagavatula
> <pbhagavatula@marvell.com>; Ankur Dwivedi <adwivedi@marvell.com>;
> Archana Muniganti <marchana@marvell.com>; Vamsi Krishna Attunuru
> <vattunuru@marvell.com>; Lukas Bartosik <lbartosik@marvell.com>; dpdk-dev
> <dev@dpdk.org>
> Subject: [EXT] Re: [dpdk-dev] [PATCH 03/15] crypto/octeontx2: configure for
> inline IPsec
> 
> External Email
> 
> ----------------------------------------------------------------------
> On Sun, Dec 8, 2019 at 5:26 PM Anoob Joseph <anoobj@marvell.com> wrote:
> >
> > From: Tejasree Kondoj <ktejasree@marvell.com>
> >
> > For enabling outbound inline IPsec, a CPT queue needs to be tied to a
> > NIX PF_FUNC. Distribute CPT queues fairly among all availble
> > otx2 eth ports.
> >
> > For inbound, one CPT LF will be assigned and initialized by kernel.
> >
> > Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
> > Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> > Signed-off-by: Archana Muniganti <marchana@marvell.com>
> > Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
> > Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
> 
> >
> > +static int
> > +otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct
> > +otx2_cpt_qp *qp) {
> > +       static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
> > +       uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
> > +       int i, ret;
> > +
> > +       for (i = 0; i < nb_ethport; i++) {
> > +               port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
> > +               if (otx2_is_ethdev(&rte_eth_devices[port_id]))
> > +                       break;
> > +       }
> > +
> > +       if (i >= nb_ethport)
> > +               return 0;
> > +
> > +       ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
> > +       if (ret)
> > +               return ret;
> > +
> > +       return 0;
> 
> Last five lines can be replaced with "return otx2_cpt_qp_ethdev_bind(dev, qp,
> port_id)"

[Anoob] In one of the following patches, one more call would be introduced after the call to otx2_cpt_qp_ethdev_bind(). So the above lines will have to be introduced anyway. For the last such addition, I'll make it return directly. Is that fine? 

> 
> Across the patch series, the above pattern is common, Please fix in all relevant
> instances.
Jerin Jacob Dec. 9, 2019, 7:53 a.m. UTC | #3
On Mon, Dec 9, 2019 at 1:22 PM Anoob Joseph <anoobj@marvell.com> wrote:
>
> Hi Jerin,
>
> Please see inline.
>
> Thanks,
> Anoob
>
> > -----Original Message-----
> > From: Jerin Jacob <jerinjacobk@gmail.com>
> > Sent: Monday, December 9, 2019 1:17 PM
> > To: Anoob Joseph <anoobj@marvell.com>
> > Cc: Akhil Goyal <akhil.goyal@nxp.com>; Declan Doherty
> > <declan.doherty@intel.com>; Thomas Monjalon <thomas@monjalon.net>;
> > Tejasree Kondoj <ktejasree@marvell.com>; Jerin Jacob Kollanukkaran
> > <jerinj@marvell.com>; Narayana Prasad Raju Athreya
> > <pathreya@marvell.com>; Kiran Kumar Kokkilagadda
> > <kirankumark@marvell.com>; Nithin Kumar Dabilpuram
> > <ndabilpuram@marvell.com>; Pavan Nikhilesh Bhagavatula
> > <pbhagavatula@marvell.com>; Ankur Dwivedi <adwivedi@marvell.com>;
> > Archana Muniganti <marchana@marvell.com>; Vamsi Krishna Attunuru
> > <vattunuru@marvell.com>; Lukas Bartosik <lbartosik@marvell.com>; dpdk-dev
> > <dev@dpdk.org>
> > Subject: [EXT] Re: [dpdk-dev] [PATCH 03/15] crypto/octeontx2: configure for
> > inline IPsec
> >
> > External Email
> >
> > ----------------------------------------------------------------------
> > On Sun, Dec 8, 2019 at 5:26 PM Anoob Joseph <anoobj@marvell.com> wrote:
> > >
> > > From: Tejasree Kondoj <ktejasree@marvell.com>
> > >
> > > For enabling outbound inline IPsec, a CPT queue needs to be tied to a
> > > NIX PF_FUNC. Distribute CPT queues fairly among all availble
> > > otx2 eth ports.
> > >
> > > For inbound, one CPT LF will be assigned and initialized by kernel.
> > >
> > > Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
> > > Signed-off-by: Anoob Joseph <anoobj@marvell.com>
> > > Signed-off-by: Archana Muniganti <marchana@marvell.com>
> > > Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
> > > Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
> >
> > >
> > > +static int
> > > +otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct
> > > +otx2_cpt_qp *qp) {
> > > +       static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
> > > +       uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
> > > +       int i, ret;
> > > +
> > > +       for (i = 0; i < nb_ethport; i++) {
> > > +               port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
> > > +               if (otx2_is_ethdev(&rte_eth_devices[port_id]))
> > > +                       break;
> > > +       }
> > > +
> > > +       if (i >= nb_ethport)
> > > +               return 0;
> > > +
> > > +       ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
> > > +       if (ret)
> > > +               return ret;
> > > +
> > > +       return 0;
> >
> > Last five lines can be replaced with "return otx2_cpt_qp_ethdev_bind(dev, qp,
> > port_id)"
>
> [Anoob] In one of the following patches, one more call would be introduced after the call to otx2_cpt_qp_ethdev_bind(). So the above lines will have to be introduced anyway. For the last such addition, I'll make it return directly. Is that fine?

Yes,

>
> >
> > Across the patch series, the above pattern is common, Please fix in all relevant
> > instances.

Patch
diff mbox series

diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
index f7d6c37..3ba67ed 100644
--- a/drivers/crypto/octeontx2/Makefile
+++ b/drivers/crypto/octeontx2/Makefile
@@ -10,7 +10,7 @@  LIB = librte_pmd_octeontx2_crypto.a
 # build flags
 CFLAGS += $(WERROR_FLAGS)
 
-LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_eal -lrte_ethdev -lrte_mbuf -lrte_mempool -lrte_ring
 LDLIBS += -lrte_cryptodev
 LDLIBS += -lrte_pci -lrte_bus_pci
 LDLIBS += -lrte_common_cpt -lrte_common_octeontx2
@@ -21,6 +21,7 @@  CFLAGS += -O3
 CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
 CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
 CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
+CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx2
 CFLAGS += -DALLOW_EXPERIMENTAL_API
 
 ifneq ($(CONFIG_RTE_ARCH_64),y)
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
index b6e5b73..67deca3 100644
--- a/drivers/crypto/octeontx2/meson.build
+++ b/drivers/crypto/octeontx2/meson.build
@@ -8,6 +8,7 @@  endif
 deps += ['bus_pci']
 deps += ['common_cpt']
 deps += ['common_octeontx2']
+deps += ['ethdev']
 name = 'octeontx2_crypto'
 
 allow_experimental_apis = true
@@ -32,3 +33,4 @@  endforeach
 includes += include_directories('../../common/cpt')
 includes += include_directories('../../common/octeontx2')
 includes += include_directories('../../mempool/octeontx2')
+includes += include_directories('../../net/octeontx2')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
index b54e407..3183210 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c
@@ -2,10 +2,13 @@ 
  * Copyright (C) 2019 Marvell International Ltd.
  */
 #include <rte_cryptodev.h>
+#include <rte_ethdev.h>
 
 #include "otx2_cryptodev.h"
+#include "otx2_cryptodev_hw_access.h"
 #include "otx2_cryptodev_mbox.h"
 #include "otx2_dev.h"
+#include "otx2_ethdev.h"
 #include "otx2_mbox.h"
 
 #include "cpt_pmd_logs.h"
@@ -173,3 +176,53 @@  otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,
 
 	return otx2_cpt_send_mbox_msg(vf);
 }
+
+int
+otx2_cpt_inline_init(const struct rte_cryptodev *dev)
+{
+	struct otx2_cpt_vf *vf = dev->data->dev_private;
+	struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+	struct cpt_rx_inline_lf_cfg_msg *msg;
+	int ret;
+
+	msg = otx2_mbox_alloc_msg_cpt_rx_inline_lf_cfg(mbox);
+	msg->sso_pf_func = otx2_sso_pf_func_get();
+
+	otx2_mbox_msg_send(mbox, 0);
+	ret = otx2_mbox_process(mbox);
+	if (ret < 0)
+		return -EIO;
+
+	return 0;
+}
+
+int
+otx2_cpt_qp_ethdev_bind(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp,
+			uint16_t port_id)
+{
+	struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];
+	struct otx2_cpt_vf *vf = dev->data->dev_private;
+	struct otx2_mbox *mbox = vf->otx2_dev.mbox;
+	struct cpt_inline_ipsec_cfg_msg *msg;
+	struct otx2_eth_dev *otx2_eth_dev;
+	int ret;
+
+	if (!otx2_is_ethdev(&rte_eth_devices[port_id]))
+		return -EINVAL;
+
+	otx2_eth_dev = otx2_eth_pmd_priv(eth_dev);
+
+	msg = otx2_mbox_alloc_msg_cpt_inline_ipsec_cfg(mbox);
+	msg->dir = CPT_INLINE_OUTBOUND;
+	msg->enable = 1;
+	msg->slot = qp->id;
+
+	msg->nix_pf_func = otx2_eth_dev->pf_func;
+
+	otx2_mbox_msg_send(mbox, 0);
+	ret = otx2_mbox_process(mbox);
+	if (ret < 0)
+		return -EIO;
+
+	return 0;
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
index a298718..ae66b08 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h
@@ -7,6 +7,8 @@ 
 
 #include <rte_cryptodev.h>
 
+#include "otx2_cryptodev_hw_access.h"
+
 int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,
 				  uint16_t *nb_queues);
 
@@ -22,4 +24,9 @@  int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,
 int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,
 			  uint64_t val);
 
+int otx2_cpt_qp_ethdev_bind(const struct rte_cryptodev *dev,
+			    struct otx2_cpt_qp *qp, uint16_t port_id);
+
+int otx2_cpt_inline_init(const struct rte_cryptodev *dev);
+
 #endif /* _OTX2_CRYPTODEV_MBOX_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index 65101b0..a1213ca 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -6,6 +6,7 @@ 
 
 #include <rte_cryptodev_pmd.h>
 #include <rte_errno.h>
+#include <rte_ethdev.h>
 
 #include "otx2_cryptodev.h"
 #include "otx2_cryptodev_capabilities.h"
@@ -125,6 +126,29 @@  otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
 	meta_info->sg_mlen = 0;
 }
 
+static int
+otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
+{
+	static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
+	uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
+	int i, ret;
+
+	for (i = 0; i < nb_ethport; i++) {
+		port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
+		if (otx2_is_ethdev(&rte_eth_devices[port_id]))
+			break;
+	}
+
+	if (i >= nb_ethport)
+		return 0;
+
+	ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 static struct otx2_cpt_qp *
 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
 		   uint8_t group)
@@ -218,6 +242,12 @@  otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
 
 	otx2_cpt_iq_disable(qp);
 
+	ret = otx2_cpt_qp_inline_cfg(dev, qp);
+	if (ret) {
+		CPT_LOG_ERR("Could not configure queue for inline IPsec");
+		goto mempool_destroy;
+	}
+
 	ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
 				 size_div40);
 	if (ret) {
@@ -857,12 +887,20 @@  otx2_cpt_dev_config(struct rte_cryptodev *dev,
 		goto queues_detach;
 	}
 
+	ret = otx2_cpt_inline_init(dev);
+	if (ret) {
+		CPT_LOG_ERR("Could not enable inline IPsec");
+		goto intr_unregister;
+	}
+
 	dev->enqueue_burst = otx2_cpt_enqueue_burst;
 	dev->dequeue_burst = otx2_cpt_dequeue_burst;
 
 	rte_mb();
 	return 0;
 
+intr_unregister:
+	otx2_cpt_err_intr_unregister(dev);
 queues_detach:
 	otx2_cpt_queues_detach(dev);
 	return ret;