From patchwork Wed Dec 11 09:52:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaojun Liu X-Patchwork-Id: 63742 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 87851A04F1; Wed, 11 Dec 2019 10:52:11 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B00D81BE84; Wed, 11 Dec 2019 10:52:09 +0100 (CET) Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-eopbgr140128.outbound.protection.outlook.com [40.107.14.128]) by dpdk.org (Postfix) with ESMTP id 3593E1BE82 for ; Wed, 11 Dec 2019 10:52:08 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XVgyxoNQU2UT0zosUPEMeIONX8msNE171GR3d6Jq0u/dYljy6Po8i9XcGdzJafY6sIJoMCVA9yjZPMivy1NqpLGDcXDh169rehfFKTeBfAL7vTMvh5zt4tQBASbJi/pD8tI1pJ/0K+PPvU3Bn5kbvLK5QERmawMsCud6EG+EJbExiwu0sw5zPGU75eeiWNLPHIOxBLhZm4M/RY0wM5+te9J378JUHDMeJeReYhWKffSf35iy7xUpPqii/alHeSZMaQCG+9c1vl/MvvSvSMes1HWgqwXxbVk+360qxkqsXfjKrC1+RNEQLMLolD7zJW3xefoFZ3eaxoMJceIFj8Fvrg== ARC-Message-Signature: i=1; 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Wed, 11 Dec 2019 09:52:01 +0000 Received: from DB7PR04MB5196.eurprd04.prod.outlook.com ([fe80::cdaa:fcae:322b:59ed]) by DB7PR04MB5196.eurprd04.prod.outlook.com ([fe80::cdaa:fcae:322b:59ed%7]) with mapi id 15.20.2516.018; Wed, 11 Dec 2019 09:52:01 +0000 From: Xiaojun Liu To: "xiao.w.wang@intel.com" , "qi.z.zhang@intel.com" , "ngai-mint.kwan@intel.com" , "jakub.fornal@intel.co" , "jacob.e.keller@intel.com" CC: "dev@dpdk.org" , Xiaojun Liu Thread-Topic: [PATCH v2 1/7] net/fm10k: add i2c sbus registers definition Thread-Index: AQHVsAiiXUXOnZQtQkuobo6TmL1rhw== Date: Wed, 11 Dec 2019 09:52:01 +0000 Message-ID: <1576057875-7677-2-git-send-email-xiaojun.liu@silicom.co.il> References: <1576057875-7677-1-git-send-email-xiaojun.liu@silicom.co.il> In-Reply-To: <1576057875-7677-1-git-send-email-xiaojun.liu@silicom.co.il> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR02CA0180.apcprd02.prod.outlook.com (2603:1096:201:21::16) To DB7PR04MB5196.eurprd04.prod.outlook.com (2603:10a6:10:1a::12) authentication-results: spf=none (sender IP is ) smtp.mailfrom=xiaojun.liu@silicom.co.il; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 1.8.3.1 x-originating-ip: [113.110.226.253] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0e655a3e-2e1e-468d-b9b5-08d77e1fc4db x-ms-traffictypediagnostic: DB7PR04MB4203: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3513; x-forefront-prvs: 024847EE92 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(346002)(366004)(136003)(39850400004)(376002)(396003)(199004)(189003)(2906002)(71200400001)(81156014)(64756008)(316002)(66556008)(6506007)(44832011)(8676002)(52116002)(81166006)(66574012)(26005)(66476007)(54906003)(110136005)(66946007)(186003)(36756003)(30864003)(6512007)(4326008)(86362001)(2616005)(107886003)(6486002)(66446008)(8936002)(5660300002)(478600001)(579004)(569006); DIR:OUT; SFP:1102; SCL:1; SRVR:DB7PR04MB4203; H:DB7PR04MB5196.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: silicom.co.il does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: d4QJsYGXTDaweov5V0lT67l5sPPJmQC2k2vR/F+qVvHr3cP9Q3Y4fWE1OSZ/IqTJkDNVpaMEk9eAgO6GBVVMqIpjAqjA6MZWl88rcrTjM3FJwTEUlkuwdtOHKq3KvtvRsJUqLGVs4F2wNbhAWCrecbdJF/ddlaPDx9ry8+JetZ/gn+OFETdE+u0xUonYJb+v7QQWvquxsnj1X7/om5EnsRX1L5u2F2yqmX2BDToIgdEgomsibQ/0EPBfP1raL3w3NVnJfCOZDmbMzIJhOJrXTlBVMlwcXyho+s3PEaE2hYgs7lDFNCiH7fVyyvlwrT36B0bAVAkYyse0/i0qpNiacaymGLS7iZgeiHFfcjtBaHaw9UmhiN0F8vHIyLCHFfbgYI4jTeMY14tHYmxhrJJU7F0Tr6BfPENTvkAQx3sAsVw4ot5H+3jThFPgtbyCoaYzMjFM7kO4Lcpetfj58MNungUkyzs1JaMhLanlIqvmYpI= MIME-Version: 1.0 X-OriginatorOrg: silicom.co.il X-MS-Exchange-CrossTenant-Network-Message-Id: 0e655a3e-2e1e-468d-b9b5-08d77e1fc4db X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Dec 2019 09:52:01.5570 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: c9e326d8-ce47-4930-8612-cc99d3c87ad1 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hLvnkyNCHRhcwIEL99ghvo/8mMZqq/xQVnkqoY/piEUJH3ui6/1Fslg5z7tDD8rg+Ai76T0xn/+GTj/aq/ZvImt3qPf6Ym8AinJW/K+xihE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4203 Subject: [dpdk-dev] [PATCH v2 1/7] net/fm10k: add i2c sbus registers definition X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To support switch management, add the following files: Add fm10k/switch/fm10k_debug.h(define log Macros). Add fm10k/switch/fm10k_regs.h(define all the registers). Add fm10k/switch/fm10k_switch.h(define switch Macros and APIs). Add fm10k/switch/fm10k_i2c.h(define I2C interfaces). Add fm10k/switch/fm10k_i2c.c(support I2C access). Add fm10k/switch/fm10k_sbus.h(define SBUS interface). Add fm10k/switch/fm10k_sbus.c(support SBUS access). and modify fm10k/Makefile(add ENABLE_FM10K_MANAGEMENT support, add fm10k_i2c.c and fm10k_sbus.c). To avoid configuration for both kernel driver and userspace SDK outside DPDK, we add switch management in FM10K DPDK PMD driver. To enable switch management, you need add CONFIG_RTE_FM10K_MANAGEMENT=y in config/common_linux when building. Signed-off-by: Xiaojun Liu --- drivers/net/fm10k/Makefile | 13 + drivers/net/fm10k/switch/fm10k_debug.h | 19 + drivers/net/fm10k/switch/fm10k_i2c.c | 310 +++++ drivers/net/fm10k/switch/fm10k_i2c.h | 54 + drivers/net/fm10k/switch/fm10k_regs.h | 2202 +++++++++++++++++++++++++++++++ drivers/net/fm10k/switch/fm10k_sbus.c | 292 ++++ drivers/net/fm10k/switch/fm10k_sbus.h | 40 + drivers/net/fm10k/switch/fm10k_switch.h | 336 +++++ 8 files changed, 3266 insertions(+) create mode 100644 drivers/net/fm10k/switch/fm10k_debug.h create mode 100644 drivers/net/fm10k/switch/fm10k_i2c.c create mode 100644 drivers/net/fm10k/switch/fm10k_i2c.h create mode 100644 drivers/net/fm10k/switch/fm10k_regs.h create mode 100644 drivers/net/fm10k/switch/fm10k_sbus.c create mode 100644 drivers/net/fm10k/switch/fm10k_sbus.h create mode 100644 drivers/net/fm10k/switch/fm10k_switch.h diff --git a/drivers/net/fm10k/Makefile b/drivers/net/fm10k/Makefile index 55e9cd5..aca6bfb 100644 --- a/drivers/net/fm10k/Makefile +++ b/drivers/net/fm10k/Makefile @@ -11,6 +11,9 @@ LIB = librte_pmd_fm10k.a CFLAGS += -O3 CFLAGS += $(WERROR_FLAGS) CFLAGS += -DALLOW_EXPERIMENTAL_API +ifeq ($(CONFIG_RTE_FM10K_MANAGEMENT),y) +CFLAGS += -DENABLE_FM10K_MANAGEMENT +endif EXPORT_MAP := rte_pmd_fm10k_version.map @@ -62,6 +65,10 @@ $(foreach obj, $(BASE_DRIVER_OBJS), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)) VPATH += $(SRCDIR)/base +ifeq ($(CONFIG_RTE_FM10K_MANAGEMENT),y) +VPATH += $(SRCDIR)/switch +endif + # # all source are stored in SRCS-y # base driver is based on the package of cid-fm10k.2017.01.24.tar.gz @@ -75,6 +82,12 @@ SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_common.c SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_mbx.c SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_vf.c SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_api.c + +ifeq ($(CONFIG_RTE_FM10K_MANAGEMENT),y) +SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_i2c.c +SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_sbus.c +endif + SRCS-$(CONFIG_RTE_LIBRTE_FM10K_INC_VECTOR) += fm10k_rxtx_vec.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/fm10k/switch/fm10k_debug.h b/drivers/net/fm10k/switch/fm10k_debug.h new file mode 100644 index 0000000..6bf72a8 --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_debug.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#ifndef _FM10K_DEBUG_H_ +#define _FM10K_DEBUG_H_ + + +#define FM10K_SW_ERR(...) PMD_INIT_LOG(ERR, __VA_ARGS__) +#define FM10K_SW_INFO(...) PMD_INIT_LOG(INFO, __VA_ARGS__) +#define FM10K_SW_TRACE(...) PMD_INIT_LOG(DEBUG, __VA_ARGS__) + +#define FM10K_SW_ASSERT(...) do {} while (0) + +#define FM10K_SW_STATS_TRACE_ENABLE 1 +#define FM10K_SW_FFU_CONF_TRACE_ENABLE 0 +#define FM10K_SW_MIRROR_TRACE_ENABLE 0 + +#endif /* _FM10K_DEBUG_H_ */ diff --git a/drivers/net/fm10k/switch/fm10k_i2c.c b/drivers/net/fm10k/switch/fm10k_i2c.c new file mode 100644 index 0000000..28b0c34 --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_i2c.c @@ -0,0 +1,310 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include "fm10k_debug.h" +#include "fm10k_i2c.h" +#include "fm10k_regs.h" +#include "fm10k_switch.h" + +static void fm10k_i2c_init(struct fm10k_i2c *); + +struct fm10k_i2c * +fm10k_i2c_attach(struct fm10k_switch *sw) +{ + struct fm10k_i2c *i2c; + + FM10K_SW_TRACE("i2c: attaching"); + + i2c = (struct fm10k_i2c *)rte_zmalloc("fm10k_i2c", + sizeof(struct fm10k_i2c), 0); + if (i2c == NULL) { + FM10K_SW_INFO("i2c: failed to allocate context"); + goto fail; + } + + i2c->sw = sw; + pthread_mutex_init(&i2c->req_lock, NULL); + pthread_mutex_init(&i2c->bus_lock, NULL); + sem_init(&i2c->req_cv, 0, 0); + + fm10k_i2c_init(i2c); + + FM10K_SW_TRACE("i2c: attach successful"); + return i2c; +fail: + if (i2c) + fm10k_i2c_detach(i2c); + return NULL; +} + +void +fm10k_i2c_detach(struct fm10k_i2c *i2c) +{ + FM10K_SW_TRACE("i2c: detaching"); + + rte_free(i2c); +} + +static void +fm10k_i2c_init(struct fm10k_i2c *i2c) +{ + struct fm10k_switch *sw = i2c->sw; + struct fm10k_device_info *cfg = sw->info; + uint32_t freq = FM10K_SW_I2C_CFG_DIVIDER_400_KHZ; + uint32_t data; + + if (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice) == + FM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4)) + freq = FM10K_SW_I2C_CFG_DIVIDER_100_KHZ; + + /* clear any pending interrupt */ + fm10k_write_switch_reg(sw, FM10K_SW_I2C_CTRL, + FM10K_SW_I2C_CTRL_INTERRUPT_PENDING); + + /* 400 KHz, master mode, unmask interrupt */ + data = fm10k_read_switch_reg(sw, FM10K_SW_I2C_CFG); + data &= ~FM10K_SW_I2C_CFG_SLAVE_ENABLE; + if (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice) == + FM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4)) + FM10K_SW_REPLACE_REG_FIELD(data, I2C_CFG_DIVIDER, freq, data); + data &= ~FM10K_SW_I2C_CFG_INTERRUPT_MASK; + fm10k_write_switch_reg(sw, FM10K_SW_I2C_CFG, data); + + if (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice) == + FM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4)) + /* reset I2C */ + fm10k_gpio_output_set(sw, 5, 1); +} + +unsigned int +fm10k_i2c_intr(struct fm10k_i2c *i2c) +{ + struct fm10k_switch *sw = i2c->sw; + struct fm10k_i2c_req *req; + int i; + uint32_t data[3]; + uint32_t ctrl; + + req = i2c->cur_req; + + FM10K_SW_SWITCH_LOCK(sw); + ctrl = fm10k_read_switch_reg(sw, FM10K_SW_I2C_CTRL); + fm10k_write_switch_reg(sw, FM10K_SW_I2C_CTRL, + FM10K_SW_I2C_CTRL_INTERRUPT_PENDING); + + req->status = FM10K_SW_REG_FIELD(ctrl, I2C_CTRL_COMMAND_COMPLETED); + + if ((req->cmd == FM10K_SW_I2C_COMMAND_RD || + req->cmd == FM10K_SW_I2C_COMMAND_WR_RD) && + req->status == FM10K_SW_I2C_COMPLETION_NORMAL) { + for (i = 0; i < FM10K_SW_HOWMANY(req->read_len, 4, 4); i++) + data[i] = fm10k_read_switch_reg + (sw, FM10K_SW_I2C_DATA(i)); + + for (i = 0; i < req->read_len; i++) + req->msg[i] = + (data[i / 4] >> (24 - (i % 4) * 8)) & 0xff; + } + FM10K_SW_SWITCH_UNLOCK(sw); + sem_post(&i2c->req_cv); + + return 1; +} + +int +fm10k_i2c_exec(struct fm10k_i2c *i2c, struct fm10k_i2c_req *req) +{ + struct fm10k_switch *sw = i2c->sw; + int i; + uint32_t ctrl; + uint32_t data[3]; + + if (((req->cmd == FM10K_SW_I2C_COMMAND_WR || + req->cmd == FM10K_SW_I2C_COMMAND_WR_RD) && + req->write_len > FM10K_SW_I2C_MSG_MAX) || + ((req->cmd == FM10K_SW_I2C_COMMAND_RD || + req->cmd == FM10K_SW_I2C_COMMAND_WR_RD) && + ((req->read_len == 0 || + req->read_len > FM10K_SW_I2C_MSG_MAX)))) + return (-1); + + FM10K_SW_TRACE("i2c: initiating command %u", req->cmd); + + ctrl = + FM10K_SW_MAKE_REG_FIELD(I2C_CTRL_ADDR, req->addr << 1) | + FM10K_SW_MAKE_REG_FIELD(I2C_CTRL_COMMAND, req->cmd); + + if (req->cmd == FM10K_SW_I2C_COMMAND_WR || + req->cmd == FM10K_SW_I2C_COMMAND_WR_RD) { + ctrl |= FM10K_SW_MAKE_REG_FIELD + (I2C_CTRL_LENGTH_W, req->write_len); + + data[0] = 0; + data[1] = 0; + data[2] = 0; + + for (i = 0; i < req->write_len; i++) + data[i / 4] |= req->msg[i] << (24 - (i % 4) * 8); + + for (i = 0; i < FM10K_SW_HOWMANY(req->write_len, 4, 4); i++) + fm10k_write_switch_reg(sw, + FM10K_SW_I2C_DATA(i), data[i]); + } + + if (req->cmd == FM10K_SW_I2C_COMMAND_RD || + req->cmd == FM10K_SW_I2C_COMMAND_WR_RD) + ctrl |= FM10K_SW_MAKE_REG_FIELD + (I2C_CTRL_LENGTH_R, req->read_len); + + req->status = FM10K_SW_I2C_COMPLETION_RUNNING; + i2c->cur_req = req; + + FM10K_SW_SWITCH_LOCK(sw); + /* zero command field */ + fm10k_write_switch_reg(sw, FM10K_SW_I2C_CTRL, 0); + /* initiate command */ + fm10k_write_switch_reg(sw, FM10K_SW_I2C_CTRL, ctrl); + FM10K_SW_SWITCH_UNLOCK(sw); + + while (req->status == FM10K_SW_I2C_COMPLETION_RUNNING) + sem_wait(&i2c->req_cv); + + return 0; +} + +int +fm10k_i2c_read8(struct fm10k_i2c *i2c, uint8_t addr, uint8_t *result) +{ + struct fm10k_i2c_req req; + int error; + + req.addr = addr; + req.cmd = FM10K_SW_I2C_COMMAND_RD; + req.read_len = 1; + req.msg[0] = 0; + + error = fm10k_i2c_exec(i2c, &req); + if (error) + goto done; + + if (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) { + FM10K_SW_INFO("i2c read failed (%u)", req.status); + error = -1; + goto done; + } + + *result = req.msg[0]; + +done: + return (error); +} + +int +fm10k_i2c_read8_ext(struct fm10k_i2c *i2c, + uint8_t addr, uint8_t reg, uint8_t *result) +{ + struct fm10k_i2c_req req; + int error; + + req.addr = addr; + req.cmd = FM10K_SW_I2C_COMMAND_WR_RD; + req.write_len = 1; + req.read_len = 1; + req.msg[0] = reg; + + error = fm10k_i2c_exec(i2c, &req); + if (error) + goto done; + + if (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) { + FM10K_SW_INFO("i2c read failed (%u)", req.status); + error = -1; + goto done; + } + + *result = req.msg[0]; +done: + return (error); +} + +int +fm10k_i2c_write8(struct fm10k_i2c *i2c, uint8_t addr, uint8_t data) +{ + struct fm10k_i2c_req req; + int error; + + req.addr = addr; + req.cmd = FM10K_SW_I2C_COMMAND_WR; + req.write_len = 1; + req.msg[0] = data; + + error = fm10k_i2c_exec(i2c, &req); + if (error) + goto done; + + if (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) { + error = -1; + goto done; + } + +done: + return (error); +} + +int +fm10k_i2c_write16(struct fm10k_i2c *i2c, + uint8_t addr, uint8_t data0, uint8_t data1) +{ + struct fm10k_i2c_req req; + int error; + + req.addr = addr; + req.cmd = FM10K_SW_I2C_COMMAND_WR; + req.write_len = 2; + req.msg[0] = data0; + req.msg[1] = data1; + + error = fm10k_i2c_exec(i2c, &req); + if (error) + goto done; + + if (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) { + error = -1; + goto done; + } +done: + return (error); +} + +int +fm10k_i2c_probe(struct fm10k_i2c *i2c, uint8_t addr) +{ + struct fm10k_i2c_req req; + int error; + + req.addr = addr; + req.cmd = FM10K_SW_I2C_COMMAND_WR; + req.write_len = 0; + + error = fm10k_i2c_exec(i2c, &req); + if (error) + goto done; + + if (req.status != FM10K_SW_I2C_COMPLETION_NORMAL) { + error = -1; + goto done; + } + +done: + return (error); +} diff --git a/drivers/net/fm10k/switch/fm10k_i2c.h b/drivers/net/fm10k/switch/fm10k_i2c.h new file mode 100644 index 0000000..f835afe --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_i2c.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#ifndef _FM10K_SW_I2C_H_ +#define _FM10K_SW_I2C_H_ + +#include +#include +#include "rte_spinlock.h" +#include "fm10k_debug.h" + +#define FM10K_SW_I2C_MSG_MAX 12 + +struct fm10k_i2c_req { + uint8_t addr; /* 7-bit address */ + uint8_t cmd; /* FM10K_SW_I2C_COMMAND_* */ + uint8_t write_len; + uint8_t read_len; + uint8_t status; /* FM10K_SW_I2C_COMPLETION_ */ + uint8_t msg[FM10K_SW_I2C_MSG_MAX]; +}; + +struct fm10k_i2c { + struct fm10k_switch *sw; + pthread_mutex_t bus_lock; + pthread_mutex_t req_lock; + sem_t req_cv; + struct fm10k_i2c_req *cur_req; +}; + +#define FM10K_SW_I2C_LOCK(i2c_) \ + pthread_mutex_lock(&(i2c_)->bus_lock) +#define FM10K_SW_I2C_UNLOCK(i2c_) \ + pthread_mutex_unlock(&(i2c_)->bus_lock) + +#define FM10K_SW_I2C_REQ_LOCK(i2c_) \ + pthread_mutex_lock(&((i2c_)->req_lock)) +#define FM10K_SW_I2C_REQ_UNLOCK(i2c_) \ + pthread_mutex_unlock(&((i2c_)->req_lock)) + +struct fm10k_i2c *fm10k_i2c_attach(struct fm10k_switch *sw); +void fm10k_i2c_detach(struct fm10k_i2c *i2c); +unsigned int fm10k_i2c_intr(struct fm10k_i2c *i2c); +int fm10k_i2c_exec(struct fm10k_i2c *i2c, struct fm10k_i2c_req *req); +int fm10k_i2c_read8(struct fm10k_i2c *i2c, uint8_t addr, uint8_t *result); +int fm10k_i2c_read8_ext(struct fm10k_i2c *i2c, + uint8_t addr, uint8_t reg, uint8_t *result); +int fm10k_i2c_write8(struct fm10k_i2c *i2c, uint8_t addr, uint8_t data); +int fm10k_i2c_write16(struct fm10k_i2c *i2c, + uint8_t addr, uint8_t data0, uint8_t data1); +int fm10k_i2c_probe(struct fm10k_i2c *i2c, uint8_t addr); + +#endif /* _FM10K_SW_I2C_H_ */ diff --git a/drivers/net/fm10k/switch/fm10k_regs.h b/drivers/net/fm10k/switch/fm10k_regs.h new file mode 100644 index 0000000..29bb95a --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_regs.h @@ -0,0 +1,2202 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#ifndef _FM10K_REGS_H_ +#define _FM10K_REGS_H_ + +#include + + +/* Convert a 32-bit word offset into a byte offset */ +#define FM10K_SW_REG_OFF(wo_) (wo_) +#define FM10K_SW_MASK32(max_bit_, min_bit_) \ + ((0xffffffffU << (min_bit_)) & \ + (0xffffffffU >> (31 - (max_bit_)))) +#define FM10K_SW_REG_FIELD(r_, name_) \ + (((uint32_t)(r_) & \ + FM10K_SW_MASK32(FM10K_SW_##name_##_msb, \ + FM10K_SW_##name_##_lsb)) >> FM10K_SW_##name_##_lsb) +#define FM10K_SW_REG_FIELD_IDX(r_, name_, i_, i1_, i2_) \ + (((uint32_t)(r_) & \ + FM10K_SW_MASK32(FM10K_SW_##name_##_msb(i_), \ + FM10K_SW_##name_##_lsb(i2_))) >> \ + FM10K_SW_##name_##_lsb(i3_)) +#define FM10K_SW_MAKE_REG_FIELD(name_, v_) \ + (((uint32_t)(v_) << FM10K_SW_##name_##_lsb) & \ + FM10K_SW_MASK32(FM10K_SW_##name_##_msb, \ + FM10K_SW_##name_##_lsb)) +#define FM10K_SW_MAKE_REG_FIELD_IDX(name_, i_, v_, i1_, i2_) \ + (((uint32_t)(v_) << FM10K_SW_##name_##_lsb(i_)) & \ + FM10K_SW_MASK32(FM10K_SW_##name_##_msb(i1_), \ + FM10K_SW_##name_##_lsb(i2_))) +#define FM10K_SW_REPLACE_REG_FIELD(r_, name_, v_, r1_) \ + (r_ = (((r1_) & \ + ~FM10K_SW_MASK32(FM10K_SW_##name_##_msb, \ + FM10K_SW_##name_##_lsb)) | \ + FM10K_SW_MAKE_REG_FIELD(name_, v_))) +#define FM10K_SW_REPLACE_REG_FIELD_IDX(r_, name_, i_, v_, r1_, i1_, i2_) \ + (r_ = (((r1_) & \ + ~FM10K_SW_MASK32(FM10K_SW_##name_##_msb(i1_), \ + FM10K_SW_##name_##_lsb(i2_))) | \ + FM10K_SW_MAKE_REG_FIELD_IDX(name_, i_, v_))) +#define FM10K_SW_MASK64(max_bit_, min_bit_) \ + ((0xffffffffffffffffULL << (min_bit_)) & \ + (0xffffffffffffffffULL >> (63 - (max_bit_)))) +#define FM10K_SW_REG_FIELD64(r_, name_) \ + (((uint64_t)(r_) & \ + FM10K_SW_MASK64(FM10K_SW_##name_##_msb64, \ + FM10K_SW_##name_##_lsb64)) >> \ + FM10K_SW_##name_##_lsb64) +#define FM10K_SW_REG_FIELD_IDX64(r_, name_, i_, i1_, i2_) \ + (((uint64_t)(r_) & \ + FM10K_SW_MASK64(FM10K_SW_##name_##_msb64(i_), \ + FM10K_SW_##name_##_lsb64(i1_))) >> \ + FM10K_SW_##name_##_lsb64(i2_)) +#define FM10K_SW_MAKE_REG_FIELD64(name_, v_) \ + (((uint64_t)(v_) << FM10K_SW_##name_##_lsb64) & \ + FM10K_SW_MASK64(FM10K_SW_##name_##_msb64, \ + FM10K_SW_##name_##_lsb64)) +#define FM10K_SW_MAKE_REG_FIELD_IDX64(name_, i_, v_, i1_, i2_) \ + (((uint64_t)(v_) << FM10K_SW_##name_##_lsb64(i_)) & \ + FM10K_SW_MASK64(FM10K_SW_##name_##_msb64(i1_), \ + FM10K_SW_##name_##_lsb64(i2_))) +#define FM10K_SW_REPLACE_REG_FIELD64(r_, name_, v_, r1_) \ + (r_ = (((r1_) & \ + ~FM10K_SW_MASK64(FM10K_SW_##name_##_msb64, \ + FM10K_SW_##name_##_lsb64)) | \ + FM10K_SW_MAKE_REG_FIELD64(name_, v_))) +#define FM10K_SW_REPLACE_REG_FIELD_IDX64(r_, name_, i_, v_, r1_, i1_, i2_) \ + (r_ = (((r1_) & \ + ~FM10K_SW_MASK64(FM10K_SW_##name_##_msb64(i1_), \ + FM10K_SW_##name_##_lsb64(i2_))) | \ + FM10K_SW_MAKE_REG_FIELD_IDX64(name_, i_, v_))) + +/* These operate on arrays of 32-bit words */ +#define FM10K_SW_SET_ARRAY_BIT(a_, name_, b_, a1_) \ + ((a_)[FM10K_SW_##name_##_bit / 32] = \ + ((a1_)[FM10K_SW_##name_##_bit / 32] & \ + ~(1 << (FM10K_SW_##name_##_bit % 32))) | \ + (((b_) & 0x1) << (FM10K_SW_##name_##_bit % 32))) + +/* Does not support fields that cross 32-bit boundaries */ +#define FM10K_SW_MAKE_ARRAY_FIELD(name_, v_) \ + (((uint32_t)(v_) << (FM10K_SW_##name_##_lsb % 32)) & \ + FM10K_SW_MASK32(FM10K_SW_##name_##_msb % 32, \ + FM10K_SW_##name_##_lsb % 32)) + +/* Does not support fields that cross 32-bit boundaries */ +#define FM10K_SW_REPLACE_ARRAY_FIELD(a_, name_, v_, a1_) \ + ((a_)[FM10K_SW_##name_##_lsb / 32] = \ + (((a1_)[FM10K_SW_##name_##_lsb / 32] & \ + ~FM10K_SW_MASK32(FM10K_SW_##name_##_msb % 32, \ + FM10K_SW_##name_##_lsb % 32)) | \ + FM10K_SW_MAKE_ARRAY_FIELD(name_, v_))) + + +/* + * BAR0 registers + */ +/* Interrupt throttle timer selection values */ +#define FM10K_SW_INT_TIMER_0 0 +#define FM10K_SW_INT_TIMER_1 1 +#define FM10K_SW_INT_TIMER_IMMEDIATE 2 +#define FM10K_SW_INT_TIMER_DISABLED 3 + +#define FM10K_SW_CTRL FM10K_SW_REG_OFF(0x0) +#define FM10K_SW_CTRL_BAR4_ALLOWED (1 << 2) +#define FM10K_SW_CTRL_EXT FM10K_SW_REG_OFF(0x1) +#define FM10K_SW_CTRL_EXT_NS_DIS (1 << 0) +#define FM10K_SW_CTRL_EXT_RO_DIS (1 << 1) +#define FM10K_SW_CTRL_EXT_SWITCH_LOOPBACK (1 << 2) +#define FM10K_SW_EXVET FM10K_SW_REG_OFF(0x2) +#define FM10K_SW_GCR FM10K_SW_REG_OFF(0x3) +#define FM10K_SW_FACTPS FM10K_SW_REG_OFF(0x4) +#define FM10K_SW_GCR_EXT FM10K_SW_REG_OFF(0x5) +#define FM10K_SW_EICR FM10K_SW_REG_OFF(0x6) +#define FM10K_SW_EICR_PCA_FAULT_SHIFT 0 +#define FM10K_SW_EICR_PCA_FAULT \ + (1 << FM10K_SW_EICR_PCA_FAULT_SHIFT) +#define FM10K_SW_EICR_THI_FAULT_SHIFT 2 +#define FM10K_SW_EICR_THI_FAULT \ + (1 << FM10K_SW_EICR_THI_FAULT_SHIFT) +#define FM10K_SW_EICR_FUM_FAULT_SHIFT 5 +#define FM10K_SW_EICR_FUM_FAULT \ + (1 << FM10K_SW_EICR_FUM_FAULT_SHIFT) +#define FM10K_SW_EICR_MAILBOX_SHIFT 6 +#define FM10K_SW_EICR_MAILBOX \ + (1 << FM10K_SW_EICR_MAILBOX_SHIFT) +#define FM10K_SW_EICR_SWITCH_READY_SHIFT 7 +#define FM10K_SW_EICR_SWITCH_READY \ + (1 << FM10K_SW_EICR_SWITCH_READY_SHIFT) +#define FM10K_SW_EICR_SWITCH_NREADY_SHIFT 8 +#define FM10K_SW_EICR_SWITCH_NREADY \ + (1 << FM10K_SW_EICR_SWITCH_NREADY_SHIFT) +#define FM10K_SW_EICR_SWITCH_INT_SHIFT 9 +#define FM10K_SW_EICR_SWITCH_INT \ + (1 << FM10K_SW_EICR_SWITCH_INT_SHIFT) +#define FM10K_SW_EICR_SRAM_ERROR_SHIFT 10 +#define FM10K_SW_EICR_SRAM_ERROR \ + (1 << FM10K_SW_EICR_SRAM_ERROR_SHIFT) +#define FM10K_SW_EICR_VFLR_SHIFT 11 +#define FM10K_SW_EICR_VFLR \ + (1 << FM10K_SW_EICR_VFLR_SHIFT) +#define FM10K_SW_EICR_MAX_HOLD_TIME_SHIFT 12 +#define FM10K_SW_EICR_MAX_HOLD_TIME \ + (1 << FM10K_SW_EICR_MAX_HOLD_TIME_SHIFT) +#define FM10K_SW_EIMR FM10K_SW_REG_OFF(0x7) +#define FM10K_SW_EIMR_DISABLE_ALL 0x55555555 +#define FM10K_SW_EIMR_NO_CHANGE 0x0 +#define FM10K_SW_EIMR_DISABLE 0x1 +#define FM10K_SW_EIMR_ENABLE 0x2 +#define FM10K_SW_EIMR_FIELD(i_, v_) \ + (FM10K_SW_EIMR_##v_ << (FM10K_SW_EICR_##i_##_SHIFT * 2)) +#define FM10K_SW_EIMR_ENABLED(e_, i_) \ + ((((e_) >> (FM10K_SW_EICR_##i_##_SHIFT * 2)) & 0x3) == \ + FM10K_SW_EIMR_ENABLE) +#define FM10K_SW_PCA_FAULT FM10K_SW_REG_OFF(0x8) +#define FM10K_SW_THI_FAULT FM10K_SW_REG_OFF(0x10) +#define FM10K_SW_FUM_FAULT FM10K_SW_REG_OFF(0x1C) +#define FM10K_SW_MAXHOLDQ(n_) FM10K_SW_REG_OFF(0x20 + (n_)) +#define FM10K_SW_MAXHOLDQ_ENTRIES 8 +#define FM10K_SW_SM_AREA FM10K_SW_REG_OFF(0x28) +#define FM10K_SW_DGLORTMAP(n_) FM10K_SW_REG_OFF(0x30 + (n_)) +#define FM10K_SW_DGLORTMAP_ENTRIES 8 +#define FM10K_SW_DGLORTMAP_MATCH_ANY 0x00000000 +#define FM10K_SW_DGLORTMAP_MATCH_NONE 0x0000ffff +#define FM10K_SW_DGLORTMAP_VALUE_lsb 0 +#define FM10K_SW_DGLORTMAP_VALUE_msb 15 +#define FM10K_SW_DGLORTMAP_MASK_lsb 16 +#define FM10K_SW_DGLORTMAP_MASK_msb 31 +#define FM10K_SW_DGLORTDEC(n_) FM10K_SW_REG_OFF(0x38 + (n_)) +#define FM10K_SW_DGLORTDEC_Q_LENGTH_lsb 0 +#define FM10K_SW_DGLORTDEC_Q_LENGTH_msb 3 +#define FM10K_SW_DGLORTDEC_VSI_LENGTH_lsb 4 +#define FM10K_SW_DGLORTDEC_VSI_LENGTH_msb 6 +#define FM10K_SW_DGLORTDEC_VSI_BASE_lsb 7 +#define FM10K_SW_DGLORTDEC_VSI_BASE_msb 13 +#define FM10K_SW_DGLORTDEC_PC_LENGTH_lsb 14 +#define FM10K_SW_DGLORTDEC_PC_LENGTH_msb 15 +#define FM10K_SW_DGLORTDEC_Q_BASE_lsb 16 +#define FM10K_SW_DGLORTDEC_Q_BASE_msb 23 +#define FM10K_SW_DGLORTDEC_RSS_LENGTH_MAX 7 +#define FM10K_SW_DGLORTDEC_RSS_LENGTH_lsb 24 +#define FM10K_SW_DGLORTDEC_RSS_LENGTH_msb 26 +#define FM10K_SW_DGLORTDEC_INNTER_RSS (1 << 27) +#define FM10K_SW_TUNNEL_CFG FM10K_SW_REG_OFF(0x40) +#define FM10K_SW_SWPRI_MAP(pri_) FM10K_SW_REG_OFF(0x50 + (pri_)) +#define FM10K_SW_RSSRK(f_, n_) \ + FM10K_SW_REG_OFF(0x800 + 0x10 * (f_) + (n_)) +#define FM10K_SW_RSSRK_ENTRIES 10 +#define FM10K_SW_RETA(f_, n_) \ + FM10K_SW_REG_OFF(0x1000 + 0x20 * (f_) + (n_)) +#define FM10K_SW_RETA_ENTRIES 32 +#define FM10K_SW_RETA_ENTRY(e0_, e1_, e2_, e3_) \ + (((e0_) & 0xff) | \ + (((e1_) & 0xff) << 8) | \ + (((e2_) & 0xff) << 16) | \ + (((e3_) & 0xff) << 24)) +#define FM10K_SW_TC_CREDIT(g_) FM10K_SW_REG_OFF(0x2000 + (g_)) +#define FM10K_SW_TC_MAXCREDIT(g_) FM10K_SW_REG_OFF(0x2040 + (g_)) +#define FM10K_SW_TC_RATE(g_) FM10K_SW_REG_OFF(0x2080 + (g_)) +#define FM10K_SW_TC_RATE_STATUS FM10K_SW_REG_OFF(0x20C0) +#define FM10K_SW_PAUSE FM10K_SW_REG_OFF(0x20C2) +#define FM10K_SW_DMA_CTRL FM10K_SW_REG_OFF(0x20C3) +#define FM10K_SW_DMA_CTRL_TX_ENABLE (1 << 0) +#define FM10K_SW_DMA_CTRL_TX_HOST_PENDING (1 << 1) +#define FM10K_SW_DMA_CTRL_TX_DATA (1 << 2) +#define FM10K_SW_DMA_CTRL_TX_ACTIVE (1 << 3) +#define FM10K_SW_DMA_CTRL_RX_ENABLE (1 << 4) +#define FM10K_SW_DMA_CTRL_RX_HOST_PENDING (1 << 5) +#define FM10K_SW_DMA_CTRL_RX_DATA (1 << 6) +#define FM10K_SW_DMA_CTRL_RX_ACTIVE (1 << 7) +#define FM10K_SW_DMA_CTRL_RX_DESC_SIZE_32 (1 << 8) +#define FM10K_SW_DMA_CTRL_MIN_MSS_lsb 9 +#define FM10K_SW_DMA_CTRL_MIN_MSS_msb 22 +#define FM10K_SW_DMA_CTRL_MAX_HOLD_TIME_lsb 23 +#define FM10K_SW_DMA_CTRL_MAX_HOLD_TIME_msb 27 +#define FM10K_SW_DMA_CTRL_DATA_PATH_RESET (1 << 29) +#define FM10K_SW_DMA_CTRL_MAX_QS_lsb 30 +#define FM10K_SW_DMA_CTRL_MAX_QS_msb 31 +#define FM10K_SW_DMA_CTRL_MAX_QS_256 0 +#define FM10K_SW_DMA_CTRL_MAX_QS_128 1 +#define FM10K_SW_DMA_CTRL_MAX_QS_64 2 +#define FM10K_SW_DMA_CTRL2 FM10K_SW_REG_OFF(0x20C4) +#define FM10K_SW_DTXTCPFLGL FM10K_SW_REG_OFF(0x20C5) +#define FM10K_SW_DTXTCPFLGH FM10K_SW_REG_OFF(0x20C6) +#define FM10K_SW_TPH_CTRL FM10K_SW_REG_OFF(0x20C7) +#define FM10K_SW_MRQC(f_) \ + FM10K_SW_REG_OFF(0x2100 + (f_)) +#define FM10K_SW_MRQC_TCPIPV4 (1 << 0) +#define FM10K_SW_MRQC_IPV4 (1 << 1) +#define FM10K_SW_MRQC_IPV6 (1 << 4) +#define FM10K_SW_MRQC_TCPIPV6 (1 << 5) +#define FM10K_SW_MRQC_UDPIPV4 (1 << 6) +#define FM10K_SW_MRQC_UDPIPV6 (1 << 7) +#define FM10K_SW_TQMAP(nvf_, vf_, vq_, vf1_, vq1_) \ + FM10K_SW_REG_OFF(0x2800 + \ + (((nvf_) & ~0x7) ? \ + ((vf_) * 32 + ((vq_) & 0x1f)) : \ + ((vf1_) * 256 + (vq1_)))) +#define FM10K_SW_RQMAP(nvf_, vf_, vq_, vf1_, vq1_) \ + FM10K_SW_REG_OFF(0x3000 + \ + (((nvf_) & ~0x7) ? \ + ((vf_) * 32 + ((vq_) & 0x1f)) : \ + ((vf1_) * 256 + (vq1_)))) +#define FM10K_SW_STATS_TIMEOUT FM10K_SW_REG_OFF(0x3800) +#define FM10K_SW_STATS_UR FM10K_SW_REG_OFF(0x3801) +#define FM10K_SW_STATS_CA FM10K_SW_REG_OFF(0x3802) +#define FM10K_SW_STATS_UM FM10K_SW_REG_OFF(0x3803) +#define FM10K_SW_STATS_XEC FM10K_SW_REG_OFF(0x3804) +#define FM10K_SW_STATS_VLAN_DROP FM10K_SW_REG_OFF(0x3805) +#define FM10K_SW_STATS_LOOPBACK_DROP FM10K_SW_REG_OFF(0x3806) +#define FM10K_SW_STATS_NODESC_DROP FM10K_SW_REG_OFF(0x3807) +#define FM10K_SW_RRTIME_CFG FM10K_SW_REG_OFF(0x3808) +#define FM10K_SW_RRTIME_LIMIT(n_) \ + FM10K_SW_REG_OFF(0x380C + 0x40 * (n_)) +#define FM10K_SW_RRTIME_COUNT(n_) \ + FM10K_SW_REG_OFF(0x3810 + 0x40 * (n_)) +#define FM10K_SW_SYSTIME FM10K_SW_REG_OFF(0x3814) +#define FM10K_SW_SYSTIME0 FM10K_SW_REG_OFF(0x3816) +#define FM10K_SW_SYSTIME_CFG FM10K_SW_REG_OFF(0x3818) +#define FM10K_SW_PFVFBME FM10K_SW_REG_OFF(0x381A) +#define FM10K_SW_PHYADDR FM10K_SW_REG_OFF(0x381C) +#define FM10K_SW_RDBAL(q_) \ + FM10K_SW_REG_OFF(0x4000 + 0x40 * (q_)) +#define FM10K_SW_RDBAH(q_) \ + FM10K_SW_REG_OFF(0x4001 + 0x40 * (q_)) +#define FM10K_SW_RDLEN(q_) \ + FM10K_SW_REG_OFF(0x4002 + 0x40 * (q_)) +#define FM10K_SW_TPH_RXCTRL(q_) \ + FM10K_SW_REG_OFF(0x4003 + 0x40 * (q_)) +#define FM10K_SW_TPH_RXCTRL_DESC_TPHEN (1 << 5) +#define FM10K_SW_TPH_RXCTRL_HEADER_TPHEN (1 << 6) +#define FM10K_SW_TPH_RXCTRL_PAYLOAD_TPHEN (1 << 7) +#define FM10K_SW_TPH_RXCTRL_DESC_READ_RO_EN (1 << 9) +#define FM10K_SW_TPH_RXCTRL_DESC_WRITE_RO_EN (1 << 11) +#define FM10K_SW_TPH_RXCTRL_DATA_WRITE_RO_EN (1 << 13) +#define FM10K_SW_TPH_RXCTRL_REP_HEADER_RO_EN (1 << 15) +#define FM10K_SW_RDH(q_) \ + FM10K_SW_REG_OFF(0x4004 + 0x40 * (q_)) +#define FM10K_SW_RDT(q_) \ + FM10K_SW_REG_OFF(0x4005 + 0x40 * (q_)) +#define FM10K_SW_RDT_RDT_lsb 0 +#define FM10K_SW_RDT_RDT_msb 15 +#define FM10K_SW_RXQCTL(q_) \ + FM10K_SW_REG_OFF(0x4006 + 0x40 * (q_)) +#define FM10K_SW_RXQCTL_ENABLE (1 << 0) +#define FM10K_SW_RXQCTL_VF_lsb 2 +#define FM10K_SW_RXQCTL_VF_msb 7 +#define FM10K_SW_RXQCTL_OWNED_BY_VF (1 << 8) +#define FM10K_SW_RXDCTL(q_) \ + FM10K_SW_REG_OFF(0x4007 + 0x40 * (q_)) +#define FM10K_SW_RXDCTL_MAX_TIME_lsb 0 +#define FM10K_SW_RXDCTL_MAX_TIME_msb 7 +#define FM10K_SW_RXDCTL_WRITE_BACK_IMM (1 << 8) +#define FM10K_SW_RXDCTL_DROP_ON_EMPTY (1 << 9) +#define FM10K_SW_RXDCTL_WRITE_RSS_HASH (1 << 10) +#define FM10K_SW_RXINT(q_) \ + FM10K_SW_REG_OFF(0x4008 + 0x40 * (q_)) +#define FM10K_SW_RXINT_INT_lsb 0 +#define FM10K_SW_RXINT_INT_msb 7 +#define FM10K_SW_RXINT_INT_TIMER_lsb 8 +#define FM10K_SW_RXINT_INT_TIMER_msb 9 +#define FM10K_SW_SRRCTL(q_) \ + FM10K_SW_REG_OFF(0x4009 + 0x40 * (q_)) +#define FM10K_SW_SRRCTL_BSIZE_PACKET_lsb 0 +#define FM10K_SW_SRRCTL_BSIZE_PACKET_msb 7 +#define FM10K_SW_SRRCTL_BSIZE_HEADER_lsb 8 +#define FM10K_SW_SRRCTL_BSIZE_HEADER_msb 13 +#define FM10K_SW_SRRCTL_DESC_TYPE_lsb 14 +#define FM10K_SW_SRRCTL_DESC_TYPE_msb 15 +#define FM10K_SW_SRRCTL_DESC_TYPE_NO_SPLIT 0 +#define FM10K_SW_SRRCTL_DESC_TYPE_HDR_SPLIT 1 +#define FM10K_SW_SRRCTL_DESC_TYPE_SIZE_SPLIT 2 +#define FM10K_SW_SRRCTL_PSR_TYPE_lsb 16 +#define FM10K_SW_SRRCTL_PSR_TYPE_msb 29 +#define FM10K_SW_SRRCTL_LOOPBACK_SUPPRESS (1 << 30) +#define FM10K_SW_SRRCTL_BUFFER_CHAINING_EN (1 << 31) +#define FM10K_SW_QPRC(q_) \ + FM10K_SW_REG_OFF(0x400A + 0x40 * (q_)) +#define FM10K_SW_QPRDC(q_) \ + FM10K_SW_REG_OFF(0x400B + 0x40 * (q_)) +#define FM10K_SW_QBRC_L(q_) \ + FM10K_SW_REG_OFF(0x400C + 0x40 * (q_)) +#define FM10K_SW_QBRC_H(q_) \ + FM10K_SW_REG_OFF(0x400D + 0x40 * (q_)) +#define FM10K_SW_RX_SGLORT(q_) \ + FM10K_SW_REG_OFF(0x400E + 0x40 * (q_)) +#define FM10K_SW_TDBAL(q_) \ + FM10K_SW_REG_OFF(0x8000 + 0x40 * (q_)) +#define FM10K_SW_TDBAH(q_) \ + FM10K_SW_REG_OFF(0x8001 + 0x40 * (q_)) +#define FM10K_SW_TDLEN(q_) \ + FM10K_SW_REG_OFF(0x8002 + 0x40 * (q_)) +#define FM10K_SW_TPH_TXCTRL(q_) \ + FM10K_SW_REG_OFF(0x8003 + 0x40 * (q_)) +#define FM10K_SW_TPH_TXCTRL_DESC_TPHEN (1 << 5) +#define FM10K_SW_TPH_TXCTRL_DESC_READ_RO_EN (1 << 9) +#define FM10K_SW_TPH_TXCTRL_DESC_WRITE_RO_EN (1 << 11) +#define FM10K_SW_TPH_TXCTRL_DATA_READ_RO_EN (1 << 13) +#define FM10K_SW_TDH(q_) \ + FM10K_SW_REG_OFF(0x8004 + 0x40 * (q_)) +#define FM10K_SW_TDT(q_) \ + FM10K_SW_REG_OFF(0x8005 + 0x40 * (q_)) +#define FM10K_SW_TDT_TDT_lsb 0 +#define FM10K_SW_TDT_TDT_msb 15 +#define FM10K_SW_TXDCTL(q_) \ + FM10K_SW_REG_OFF(0x8006 + 0x40 * (q_)) +#define FM10K_SW_TXDCTL_PTHRESH_lsb 0 +#define FM10K_SW_TXDCTL_PTHRESH_msb 6 +#define FM10K_SW_TXDCTL_HTHRESH_lsb 7 +#define FM10K_SW_TXDCTL_HTHRESH_msb 13 +#define FM10K_SW_TXDCTL_ENABLE (1 << 14) +#define FM10K_SW_TXDCTL_MAX_TIME_lsb 16 +#define FM10K_SW_TXDCTL_MAX_TIME_msb 27 +#define FM10K_SW_TXDCTL_PUSH_DESC (1 << 28) +#define FM10K_SW_TXQCTL(q_) \ + FM10K_SW_REG_OFF(0x8007 + 0x40 * (q_)) +#define FM10K_SW_TXQCTL_VF_lsb 0 +#define FM10K_SW_TXQCTL_VF_msb 5 +#define FM10K_SW_TXQCTL_OWNED_BY_VF (1 << 6) +#define FM10K_SW_TXQCTL_PC_lsb 7 +#define FM10K_SW_TXQCTL_PC_msb 9 +#define FM10K_SW_TXQCTL_TC_lsb 10 +#define FM10K_SW_TXQCTL_TC_msb 15 +#define FM10K_SW_TXQCTL_VID_lsb 16 +#define FM10K_SW_TXQCTL_VID_msb 27 +#define FM10K_SW_TXQCTL_UNLIMITED_BW (1 << 28) +#define FM10K_SW_TXQCTL_PUSH_MODE_DIS (1 << 29) +#define FM10K_SW_TXINT(q_) \ + FM10K_SW_REG_OFF(0x8008 + 0x40 * (q_)) +#define FM10K_SW_TXINT_INT_lsb 0 +#define FM10K_SW_TXINT_INT_msb 7 +#define FM10K_SW_TXINT_INT_TIMER_lsb 8 +#define FM10K_SW_TXINT_INT_TIMER_msb 9 +#define FM10K_SW_QPTC(q_) \ + FM10K_SW_REG_OFF(0x8009 + 0x40 * (q_)) +#define FM10K_SW_QBTC_L(q_) \ + FM10K_SW_REG_OFF(0x800A + 0x40 * (q_)) +#define FM10K_SW_QBTC_H(q_) \ + FM10K_SW_REG_OFF(0x800B + 0x40 * (q_)) +#define FM10K_SW_TQDLOC(q_) \ + FM10K_SW_REG_OFF(0x800C + 0x40 * (q_)) +#define FM10K_SW_TQDLOC_BASE_lsb 0 +#define FM10K_SW_TQDLOC_BASE_msb 15 +#define FM10K_SW_TQDLOC_SIZE_lsb 16 +#define FM10K_SW_TQDLOC_SIZE_msb 19 +#define FM10K_SW_TQDLOC_SIZE_32 5 +#define FM10K_SW_TQDLOC_SIZE_64 6 +#define FM10K_SW_TQDLOC_SIZE_128 7 +#define FM10K_SW_TX_SGLORT(q_) \ + FM10K_SW_REG_OFF(0x800D + 0x40 * (q_)) +#define FM10K_SW_TX_SGLORT_SGLORT_lsb 0 +#define FM10K_SW_TX_SGLORT_SGLORT_msb 15 +#define FM10K_SW_PFVTCTL(q_) \ + FM10K_SW_REG_OFF(0x800E + 0x40 * (q_)) +#define FM10K_SW_TX_DESC(q_, d_, w_) \ + FM10K_SW_REG_OFF(0x40000 + \ + 0x400 * (q_) + 0x4 * (d_) + (w_)) +#define FM10K_SW_PBACL(n_) \ + FM10K_SW_REG_OFF(0x10000 + (n_)) +#define FM10K_SW_INT_MAP(n_) \ + FM10K_SW_REG_OFF(0x10080 + (n_)) +#define FM10K_SW_INT_MAP_ENTRIES 8 +#define FM10K_SW_INT_MAP_INDEX_MAILBOX 0 +#define FM10K_SW_INT_MAP_INDEX_FAULT 1 +#define FM10K_SW_INT_MAP_INDEX_SWITCH_UP_DOWN 2 +#define FM10K_SW_INT_MAP_INDEX_SWITCH 3 +#define FM10K_SW_INT_MAP_INDEX_SRAM 4 +#define FM10K_SW_INT_MAP_INDEX_VFLR 5 +#define FM10K_SW_INT_MAP_INDEX_MAX_HOLD_TIME 6 +#define FM10K_SW_INT_MAP_INT_lsb 0 +#define FM10K_SW_INT_MAP_INT_msb 7 +#define FM10K_SW_INT_MAP_INT_TIMER_lsb 8 +#define FM10K_SW_INT_MAP_INT_TIMER_msb 9 +#define FM10K_SW_MSIX_VECTOR(v_) \ + FM10K_SW_REG_OFF(0x11000 + 0x4 * (v_)) +#define FM10K_SW_INT_CTRL \ + FM10K_SW_REG_OFF(0x12000) +#define FM10K_SW_INT_CTRL_NEXT_VECTOR_lsb 0 +#define FM10K_SW_INT_CTRL_NEXT_VECTOR_msb 9 +#define FM10K_SW_INT_CTRL_ENABLE_MODERATOR (1 << 10) +#define FM10K_SW_ITR(v_) \ + FM10K_SW_REG_OFF(0x12400 + (v_)) + +/* + * Interrupt throttle timer intervals in microseconds. These provide the + * direct values for programming the ITR interval field when using a Gen3 + * PCLK, otherwise they need to be scaled appropriately. + */ +#define FM10K_SW_ITR_INTERVAL_20K 50 +#define FM10K_SW_ITR_INTERVAL_40K 25 +#define FM10K_SW_ITR_INTERVAL_0_lsb 0 +#define FM10K_SW_ITR_INTERVAL_0_msb 11 +#define FM10K_SW_ITR_INTERVAL_1_lsb 12 +#define FM10K_SW_ITR_INTERVAL_1_msb 23 +#define FM10K_SW_ITR_TIMER_0_EXPIRED (1 << 24) +#define FM10K_SW_ITR_TIMER_1_EXPIRED (1 << 25) +#define FM10K_SW_ITR_PENDING_0 (1 << 26) +#define FM10K_SW_ITR_PENDING_1 (1 << 27) +#define FM10K_SW_ITR_PENDING_2 (1 << 28) +#define FM10K_SW_ITR_AUTO_MASK (1 << 29) +#define FM10K_SW_ITR_MASK_lsb 30 +#define FM10K_SW_ITR_MASK_msb 31 +#define FM10K_SW_ITR_MASK_R_ENABLED 0 +#define FM10K_SW_ITR_MASK_R_BLOCKED 1 +#define FM10K_SW_ITR_MASK_W_KEEP 0 +#define FM10K_SW_ITR_MASK_W_BLOCK 1 +#define FM10K_SW_ITR_MASK_W_ENABLE 2 +#define FM10K_SW_ITR2(v_) \ + FM10K_SW_REG_OFF(0x12800 + 0x2 * (v_)) +#define FM10K_SW_IP \ + FM10K_SW_REG_OFF(0x13000) +#define FM10K_SW_IP_HOT_RESET (1 << 0) +#define FM10K_SW_IP_DEVICE_STATE_CHANGE (1 << 1) +#define FM10K_SW_IP_MAILBOX (1 << 2) +#define FM10K_SW_IP_VPD_REQUEST (1 << 3) +#define FM10K_SW_IP_SRAM_ERROR (1 << 4) +#define FM10K_SW_IP_PFLR (1 << 5) +#define FM10K_SW_IP_DATA_PATH_RESET (1 << 6) +#define FM10K_SW_IP_OUT_OF_RESET (1 << 7) +#define FM10K_SW_IP_NOT_IN_RESET (1 << 8) +#define FM10K_SW_IP_TIMEOUT (1 << 9) +#define FM10K_SW_IP_VFLR (1 << 10) +#define FM10K_SW_IM \ + FM10K_SW_REG_OFF(0x13001) +#define FM10K_SW_IM_ALL \ + FM10K_SW_MASK32(10, 0) +#define FM10K_SW_IM_HOT_RESET (1 << 0) +#define FM10K_SW_IM_DEVICE_STATE_CHANGE (1 << 1) +#define FM10K_SW_IM_MAILBOX (1 << 2) +#define FM10K_SW_IM_VPD_REQUEST (1 << 3) +#define FM10K_SW_IM_SRAM_ERROR (1 << 4) +#define FM10K_SW_IM_PFLR (1 << 5) +#define FM10K_SW_IM_DATA_PATH_RESET (1 << 6) +#define FM10K_SW_IM_OUT_OF_RESET (1 << 7) +#define FM10K_SW_IM_TIMEOUT (1 << 9) +#define FM10K_SW_IM_VFLR (1 << 10) +#define FM10K_SW_IB FM10K_SW_REG_OFF(0x13002) +#define FM10K_SW_SRAM_IP FM10K_SW_REG_OFF(0x13003) +#define FM10K_SW_SRAM_IM FM10K_SW_REG_OFF(0x13004) +#define FM10K_SW_VLAN_TABLE(f_) \ + FM10K_SW_REG_OFF(0x14000 + 0x80 * (f_)) +#define FM10K_SW_VLAN_TABLE_ENTRIES 128 +#define FM10K_SW_VLAN_TABLE_ENTRY(f_, n_) \ + FM10K_SW_REG_OFF(0x14000 + 0x80 * (f_) + (n_)) +#define FM10K_SW_VLAN_TABLE_VLAN_ENTRY(f_, vl_) \ + FM10K_SW_REG_OFF(0x14000 + 0x80 * (f_) + ((vl_) >> 5)) +#define FM10K_SW_VLAN_TABLE_VLAN_BIT(vl_) (1 << ((vl_) & 0x1f)) +#define FM10K_SW_MBMEM(n_) \ + FM10K_SW_REG_OFF(0x18000 + (n_)) +#define FM10K_SW_MBX(vf_) \ + FM10K_SW_REG_OFF(0x18800 + (vf_)) +#define FM10K_SW_MBICR(vf_) \ + FM10K_SW_REG_OFF(0x18840 + ((vf_) >> 5)) +#define FM10K_SW_GMBX FM10K_SW_REG_OFF(0x18842) +#define FM10K_SW_GMBX_GLOBAL_REQ (1 << 1) +#define FM10K_SW_GMBX_GLOBAL_ACK (1 << 2) +#define FM10K_SW_GMBX_PF_REQ_INTERRUPT (1 << 3) +#define FM10K_SW_GMBX_PF_ACK_INTERRUPT (1 << 4) +#define FM10K_SW_GMBX_PF_INTERRUPT_ENABLE_lsb 5 +#define FM10K_SW_GMBX_PF_INTERRUPT_ENABLE_msb 6 +#define FM10K_SW_GMBX_INTERRUPT_NO_CHANGE 0 +#define FM10K_SW_GMBX_INTERRUPT_ENABLE 1 +#define FM10K_SW_GMBX_INTERRUPT_DISABLE 2 +#define FM10K_SW_GMBX_PF_REQ (1 << 7) +#define FM10K_SW_GMBX_PF_ACK (1 << 8) +#define FM10K_SW_GMBX_GLOBAL_REQ_INTERRUPT (1 << 9) +#define FM10K_SW_GMBX_GLOBAL_ACK_INTERRUPT (1 << 10) +#define FM10K_SW_GMBX_GLOBAL_INTERRUPT_ENABLE_lsb 11 +#define FM10K_SW_GMBX_GLOBAL_INTERRUPT_ENABLE_msb 12 +#define FM10K_SW_PFVFLRE FM10K_SW_REG_OFF(0x18844) +#define FM10K_SW_PFVFLREC FM10K_SW_REG_OFF(0x18846) +#define FM10K_SW_TEST_CFG0 FM10K_SW_REG_OFF(0x18849) +#define FM10K_SW_INT_SRAM_CTRL FM10K_SW_REG_OFF(0x18850) +#define FM10K_SW_FUM_SRAM_CTRL FM10K_SW_REG_OFF(0x18852) +#define FM10K_SW_PCA_SRAM_CTRL FM10K_SW_REG_OFF(0x18854) +#define FM10K_SW_PP_SRAM_CTRL FM10K_SW_REG_OFF(0x18858) +#define FM10K_SW_PCW_SRAM_CTRL FM10K_SW_REG_OFF(0x1885C) +#define FM10K_SW_RHI_SRAM_CTRL1 FM10K_SW_REG_OFF(0x18872) +#define FM10K_SW_RHI_SRAM_CTRL2 FM10K_SW_REG_OFF(0x18860) +#define FM10K_SW_THI_SRAM_CTRL1 FM10K_SW_REG_OFF(0x18864) +#define FM10K_SW_THI_SRAM_CTRL2 FM10K_SW_REG_OFF(0x18868) +#define FM10K_SW_TIMEOUT_CFG FM10K_SW_REG_OFF(0x1886B) +#define FM10K_SW_LVMMC FM10K_SW_REG_OFF(0x18880) +#define FM10K_SW_LVMMI FM10K_SW_REG_OFF(0x18881) +#define FM10K_SW_HOST_MISC FM10K_SW_REG_OFF(0x19000) +#define FM10K_SW_HOST_LANE_CTRL FM10K_SW_REG_OFF(0x19001) +#define FM10K_SW_SERDES_CTRL(l_) \ + FM10K_SW_REG_OFF(0x19010 + 0x2 * (l_)) + +/* + * BAR4 registers + */ + +/* + * Access to non-master PEP registers via BAR4 + */ +#define FM10K_SW_PCIE_GLOBAL(p_, r_) \ + (FM10K_SW_REG_OFF(((p_) + 1) << 20) | FM10K_SW_##r_) + +/* + * SBUS register fields for use with both the PCIE and EPL SBUS interfaces. + */ +#define FM10K_SW_SBUS_CFG_SBUS_CONTROLLER_RESET (1 << 0) +#define FM10K_SW_SBUS_CFG_ROM_ENABLE (1 << 1) +#define FM10K_SW_SBUS_CFG_ROM_BUSY (1 << 2) +#define FM10K_SW_SBUS_CFG_BIST_DONE_PASS (1 << 3) +#define FM10K_SW_SBUS_CFG_BIST_DONE_FAIL (1 << 4) + +#define FM10K_SW_SBUS_COMMAND_REGISTER_lsb 0 +#define FM10K_SW_SBUS_COMMAND_REGISTER_msb 7 +#define FM10K_SW_SBUS_COMMAND_ADDRESS_lsb 8 +#define FM10K_SW_SBUS_COMMAND_ADDRESS_msb 15 +#define FM10K_SW_SBUS_COMMAND_OP_lsb 16 +#define FM10K_SW_SBUS_COMMAND_OP_msb 23 +#define FM10K_SW_SBUS_OP_RESET 0x20 +#define FM10K_SW_SBUS_OP_WRITE 0x21 +#define FM10K_SW_SBUS_OP_READ 0x22 +#define FM10K_SW_SBUS_COMMAND_EXECUTE (1 << 24) +#define FM10K_SW_SBUS_COMMAND_BUSY (1 << 25) +#define FM10K_SW_SBUS_COMMAND_RESULT_CODE_lsb 26 +#define FM10K_SW_SBUS_COMMAND_RESULT_CODE_msb 28 +#define FM10K_SW_SBUS_RESULT_RESET 0x00 +#define FM10K_SW_SBUS_RESULT_WRITE 0x01 +#define FM10K_SW_SBUS_RESULT_READ 0x04 + +#define FM10K_SW_SBUS_ADDR_EPL_RMON2 1 +#define FM10K_SW_SBUS_ADDR_EPL_LANE(e_, l_) (4 * (e_) + (l_) + 2) +#define FM10K_SW_SBUS_ADDR_EPL_SERDES(s_) ((s_) + 2) +#define FM10K_SW_SBUS_ADDR_EPL_RMON3 38 +#define FM10K_SW_SBUS_ADDR_EPL_PMRO 39 + +/* Common to both EPL and PCIE + */ +#define FM10K_SW_SBUS_ADDR_SPICO 253 +#define FM10K_SW_SBUS_ADDR_SBUS_CONTROLLER 254 +#define FM10K_SW_SBUS_ADDR_BROADCAST 0xFF + + +#define FM10K_SW_MGMT_BASE \ + FM10K_SW_REG_OFF(0x000000) +#define FM10K_SW_MGMT_REG(wo_) \ + (FM10K_SW_MGMT_BASE + FM10K_SW_REG_OFF(wo_)) + +#define FM10K_SW_FATAL_CODE FM10K_SW_MGMT_REG(0x0) +#define FM10K_SW_LAST_FATAL_CODE FM10K_SW_MGMT_REG(0x1) +#define FM10K_SW_FATAL_COUNT FM10K_SW_MGMT_REG(0x2) +#define FM10K_SW_SOFT_RESET FM10K_SW_MGMT_REG(0x3) +#define FM10K_SW_SOFT_RESET_COLD_RESET (1 << 0) +#define FM10K_SW_SOFT_RESET_EPL_RESET (1 << 1) +#define FM10K_SW_SOFT_RESET_SWITCH_RESET (1 << 2) +#define FM10K_SW_SOFT_RESET_SWITCH_READY (1 << 3) +#define FM10K_SW_SOFT_RESET_PCIE_RESET(p_) (1 << ((p_) + 4)) +#define FM10K_SW_SOFT_RESET_PCIE_ACTIVE(p_) (1 << ((p_) + 13)) +#define FM10K_SW_DEVICE_CFG FM10K_SW_MGMT_REG(0x4) +#define FM10K_SW_DEVICE_CFG_PCIE_MODE_PAIRS 4 +#define FM10K_SW_DEVICE_CFG_PCIE_MODE_2X4(p_) (1 << (p_)) +#define FM10K_SW_DEVICE_CFG_PCIE_100G_DIS (1 << 4) +#define FM10K_SW_DEVICE_CFG_FEATURE_lsb 5 +#define FM10K_SW_DEVICE_CFG_FEATURE_msb 6 +#define FM10K_SW_DEVICE_CFG_PCIE_FULL 0 +#define FM10K_SW_DEVICE_CFG_PCIE_HALF 1 +#define FM10K_SW_DEVICE_CFG_PCIE_BASIC 2 +#define FM10K_SW_DEVICE_CFG_PCIE_EN(p_) (1 << (7 + (p_))) +#define FM10K_SW_RESET_CFG FM10K_SW_MGMT_REG(0x5) +#define FM10K_SW_WATCHDOG_CFG FM10K_SW_MGMT_REG(0x6) +#define FM10K_SW_MGMT_SCRATCH(n_) FM10K_SW_MGMT_REG(0x8 + (n_)) +#define FM10K_SW_VITAL_PRODUCT_DATA FM10K_SW_MGMT_REG(0x304) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT FM10K_SW_MGMT_REG(0x400) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_BSM_lsb64 0 +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_BSM_msb64 8 +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_BSM(n_) (1ULL << (n_)) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_lsb64 9 +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE_msb64 17 +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PCIE(n_) \ + (1ULL << ((n_) + 9)) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_EPL_lsb64 18 +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_EPL_msb64 26 +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_EPL(n_) \ + (1ULL << ((n_) + 18)) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_TUNNEL_lsb64 27 +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_TUNNEL_msb64 28 +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_TUNNEL(n_) \ + (1ULL << ((n_) + 27)) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_CORE (1ULL << 29) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_SOFTWARE (1ULL << 30) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_GPIO (1ULL << 31) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_I2C (1ULL << 32) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_MDIO (1ULL << 33) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_CRM (1ULL << 34) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_FH_TAIL (1ULL << 35) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_FH_HEAD (1ULL << 36) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_SBUS_EPL (1ULL << 37) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_SBUS_PCIE (1ULL << 38) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_PINS (1ULL << 39) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_FIBM (1ULL << 40) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_BSM (1ULL << 41) +#define FM10K_SW_GLOBAL_INTERRUPT_DETECT_XCLK (1ULL << 42) +#define FM10K_SW_INTERRUPT_MASK_INT \ + FM10K_SW_MGMT_REG(0x402) +#define FM10K_SW_INTERRUPT_MASK_PCIE(p_) \ + FM10K_SW_MGMT_REG(0x420 + 0x2 * (p_)) +#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_BSM_lsb64 0 +#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_BSM_msb64 8 +#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_BSM(n_) (1ULL << (n_)) +#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_lsb64 9 +#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE_msb64 17 +#define FM10K_SW_INTERRUPT_MASK_PCIE_PCIE(n_) \ + (1ULL << ((n_) + 9)) +#define FM10K_SW_INTERRUPT_MASK_PCIE_EPL_lsb64 18 +#define FM10K_SW_INTERRUPT_MASK_PCIE_EPL_msb64 26 +#define FM10K_SW_INTERRUPT_MASK_PCIE_EPL(n_) \ + (1ULL << ((n_) + 18)) +#define FM10K_SW_INTERRUPT_MASK_PCIE_TUNNEL_lsb64 27 +#define FM10K_SW_INTERRUPT_MASK_PCIE_TUNNEL_msb64 28 +#define FM10K_SW_INTERRUPT_MASK_PCIE_TUNNEL(n_) \ + (1ULL << ((n_) + 27)) +#define FM10K_SW_INTERRUPT_MASK_PCIE_CORE (1ULL << 29) +#define FM10K_SW_INTERRUPT_MASK_PCIE_SOFTWARE (1ULL << 30) +#define FM10K_SW_INTERRUPT_MASK_PCIE_GPIO (1ULL << 31) +#define FM10K_SW_INTERRUPT_MASK_PCIE_I2C (1ULL << 32) +#define FM10K_SW_INTERRUPT_MASK_PCIE_MDIO (1ULL << 33) +#define FM10K_SW_INTERRUPT_MASK_PCIE_CRM (1ULL << 34) +#define FM10K_SW_INTERRUPT_MASK_PCIE_FH_TAIL (1ULL << 35) +#define FM10K_SW_INTERRUPT_MASK_PCIE_FH_HEAD (1ULL << 36) +#define FM10K_SW_INTERRUPT_MASK_PCIE_SBUS_EPL (1ULL << 37) +#define FM10K_SW_INTERRUPT_MASK_PCIE_SBUS_PCIE (1ULL << 38) +#define FM10K_SW_INTERRUPT_MASK_PCIE_PINS (1ULL << 39) +#define FM10K_SW_INTERRUPT_MASK_PCIE_FIBM (1ULL << 40) +#define FM10K_SW_INTERRUPT_MASK_PCIE_BSM (1ULL << 41) +#define FM10K_SW_INTERRUPT_MASK_PCIE_XCLK (1ULL << 42) +#define FM10K_SW_INTERRUPT_MASK_PCIE_ALL FM10K_SW_MASK64(42, 0) +#define FM10K_SW_INTERRUPT_MASK_FIBM FM10K_SW_MGMT_REG(0x440) +#define FM10K_SW_INTERRUPT_MASK_BSM FM10K_SW_MGMT_REG(0x442) +#define FM10K_SW_CORE_INTERRUPT_DETECT FM10K_SW_MGMT_REG(0x444) +#define FM10K_SW_CORE_INTERRUPT_MASK FM10K_SW_MGMT_REG(0x445) +#define FM10K_SW_SRAM_ERR_IP FM10K_SW_MGMT_REG(0x446) +#define FM10K_SW_SRAM_ERR_IM FM10K_SW_MGMT_REG(0x448) +#define FM10K_SW_PINS_STAT FM10K_SW_MGMT_REG(0x44A) +#define FM10K_SW_PINS_IP FM10K_SW_MGMT_REG(0x44B) +#define FM10K_SW_PINS_IM FM10K_SW_MGMT_REG(0x44C) +#define FM10K_SW_SW_IP FM10K_SW_MGMT_REG(0x44D) +#define FM10K_SW_SW_IM FM10K_SW_MGMT_REG(0x44E) +#define FM10K_SW_SW_TEST_AND_SET FM10K_SW_MGMT_REG(0x44F) +#define FM10K_SW_LSM_CLKOBS_CTRL FM10K_SW_MGMT_REG(0x450) +#define FM10K_SW_CHIP_VERSION FM10K_SW_MGMT_REG(0x452) +#define FM10K_SW_BSM_SCRATCH(n_) FM10K_SW_MGMT_REG(0x800 + (n_)) +#define FM10K_SW_BSM_CTRL FM10K_SW_MGMT_REG(0xC00) +#define FM10K_SW_BSM_ARGS FM10K_SW_MGMT_REG(0xC01) +#define FM10K_SW_BSM_ADDR_OFFSET(n_) FM10K_SW_MGMT_REG(0xC04 + (n_)) +#define FM10K_SW_BSM_COUNTER(n_) FM10K_SW_MGMT_REG(0xC08 + (n_)) +#define FM10K_SW_BSM_SRAM_CTRL FM10K_SW_MGMT_REG(0xC0A) +#define FM10K_SW_BSM_IP FM10K_SW_MGMT_REG(0xC0B) +#define FM10K_SW_BSM_IM FM10K_SW_MGMT_REG(0xC0C) +#define FM10K_SW_PIN_STRAP_STAT FM10K_SW_MGMT_REG(0xC0D) +#define FM10K_SW_FUSE_DATA_0 FM10K_SW_MGMT_REG(0xC0E) +#define FM10K_SW_FUSE_SKU_lsb 11 +#define FM10K_SW_FUSE_SKU_msb 15 +#define FM10K_SW_FUSE_SKU_FM10840 0 +#define FM10K_SW_FUSE_SKU_FM10420 1 +#define FM10K_SW_FUSE_SKU_FM10064 2 +#define FM10K_SW_FUSE_DATA_1 FM10K_SW_MGMT_REG(0xC0F) +#define FM10K_SW_BIST_CTRL FM10K_SW_MGMT_REG(0xC10) +#define FM10K_SW_BIST_CTRL_BIST_RUN_PCIE(p_) (1ULL << (p_)) +#define FM10K_SW_BIST_CTRL_BIST_RUN_EPL (1ULL << 9) +#define FM10K_SW_BIST_CTRL_BIST_RUN_FABRIC (1ULL << 10) +#define FM10K_SW_BIST_CTRL_BIST_RUN_TUNNEL (1ULL << 11) +#define FM10K_SW_BIST_CTRL_BIST_RUN_BSM (1ULL << 12) +#define FM10K_SW_BIST_CTRL_BIST_RUN_CRM (1ULL << 13) +#define FM10K_SW_BIST_CTRL_BIST_RUN_FIBM (1ULL << 14) +#define FM10K_SW_BIST_CTRL_BIST_RUN_SBM (1ULL << 15) +#define FM10K_SW_BIST_CTRL_BIST_MODE_PCIE(p_) (1ULL << (p_)) +#define FM10K_SW_BIST_CTRL_BIST_MODE_EPL (1ULL << 41) +#define FM10K_SW_BIST_CTRL_BIST_MODE_FABRIC (1ULL << 42) +#define FM10K_SW_BIST_CTRL_BIST_MODE_TUNNEL (1ULL << 43) +#define FM10K_SW_BIST_CTRL_BIST_MODE_BSM (1ULL << 44) +#define FM10K_SW_BIST_CTRL_BIST_MODE_CRM (1ULL << 45) +#define FM10K_SW_BIST_CTRL_BIST_MODE_FIBM (1ULL << 46) +#define FM10K_SW_BIST_CTRL_BIST_MODE_SBM (1ULL << 47) +#define FM10K_SW_REI_CTRL FM10K_SW_MGMT_REG(0xC12) +#define FM10K_SW_REI_STAT FM10K_SW_MGMT_REG(0xC13) +#define FM10K_SW_GPIO_CFG FM10K_SW_MGMT_REG(0xC15) +#define FM10K_SW_GPIO_DATA FM10K_SW_MGMT_REG(0xC16) +#define FM10K_SW_GPIO_IP FM10K_SW_MGMT_REG(0xC17) +#define FM10K_SW_GPIO_IM FM10K_SW_MGMT_REG(0xC18) +#define FM10K_SW_I2C_CFG FM10K_SW_MGMT_REG(0xC19) +#define FM10K_SW_I2C_CFG_SLAVE_ENABLE (1 << 0) +#define FM10K_SW_I2C_CFG_ADDR_lsb 1 +#define FM10K_SW_I2C_CFG_ADDR_msb 7 +#define FM10K_SW_I2C_CFG_DIVIDER_lsb 8 +#define FM10K_SW_I2C_CFG_DIVIDER_msb 19 +#define FM10K_SW_I2C_CFG_DIVIDER_100_KHZ 52 +#define FM10K_SW_I2C_CFG_DIVIDER_400_KHZ 10 +#define FM10K_SW_I2C_CFG_INTERRUPT_MASK (1 << 20) +#define FM10K_SW_I2C_CFG_DEBOUNCE_FILTER_COUNT_LIMIT_lsb 21 +#define FM10K_SW_I2C_CFG_DEBOUNCE_FILTER_COUNT_LIMIT_msb 27 +#define FM10K_SW_I2C_DATA(n_) FM10K_SW_MGMT_REG(0xC1C + (n_)) +#define FM10K_SW_I2C_CTRL FM10K_SW_MGMT_REG(0xC20) +#define FM10K_SW_I2C_CTRL_ADDR_lsb 0 +#define FM10K_SW_I2C_CTRL_ADDR_msb 7 +#define FM10K_SW_I2C_CTRL_COMMAND_lsb 8 +#define FM10K_SW_I2C_CTRL_COMMAND_msb 9 +#define FM10K_SW_I2C_COMMAND_NULL 0 +#define FM10K_SW_I2C_COMMAND_WR 1 +#define FM10K_SW_I2C_COMMAND_WR_RD 2 +#define FM10K_SW_I2C_COMMAND_RD 3 +#define FM10K_SW_I2C_CTRL_LENGTH_W_lsb 10 +#define FM10K_SW_I2C_CTRL_LENGTH_W_msb 13 +#define FM10K_SW_I2C_CTRL_LENGTH_R_lsb 14 +#define FM10K_SW_I2C_CTRL_LENGTH_R_msb 17 +#define FM10K_SW_I2C_CTRL_LENGTH_SENT_lsb 18 +#define FM10K_SW_I2C_CTRL_LENGTH_SENT_msb 21 +#define FM10K_SW_I2C_CTRL_COMMAND_COMPLETED_lsb 22 +#define FM10K_SW_I2C_CTRL_COMMAND_COMPLETED_msb 25 +#define FM10K_SW_I2C_COMPLETION_RUNNING 0 +#define FM10K_SW_I2C_COMPLETION_NORMAL 1 +#define FM10K_SW_I2C_COMPLETION_PREMATURE 2 +#define FM10K_SW_I2C_COMPLETION_NO_DEVICE 3 +#define FM10K_SW_I2C_COMPLETION_TIMEOUT 4 +#define FM10K_SW_I2C_COMPLETION_LOST_ARB 5 +#define FM10K_SW_I2C_COMPLETION_BUS_WAIT 6 +#define FM10K_SW_I2C_COMPLETION_INVALID 7 +#define FM10K_SW_I2C_CTRL_INTERRUPT_PENDING (1 << 26) +#define FM10K_SW_MDIO_CFG FM10K_SW_MGMT_REG(0xC22) +#define FM10K_SW_MDIO_DATA FM10K_SW_MGMT_REG(0xC23) +#define FM10K_SW_MDIO_CTRL FM10K_SW_MGMT_REG(0xC24) +#define FM10K_SW_SPI_TX_DATA FM10K_SW_MGMT_REG(0xC26) +#define FM10K_SW_SPI_RX_DATA FM10K_SW_MGMT_REG(0xC27) +#define FM10K_SW_SPI_HEADER FM10K_SW_MGMT_REG(0xC28) +#define FM10K_SW_SPI_CTRL FM10K_SW_MGMT_REG(0xC29) +#define FM10K_SW_LED_CFG FM10K_SW_MGMT_REG(0xC2B) +#define FM10K_SW_SCAN_DATA_IN FM10K_SW_MGMT_REG(0xC2D) +#define FM10K_SW_SCAN_DATA_IN_SCAN_DATA_lsb 0 +#define FM10K_SW_SCAN_DATA_IN_SCAN_DATA_msb 24 +#define FM10K_SW_SCAN_DATA_IN_SHIFT_IN (1 << 25) +#define FM10K_SW_SCAN_DATA_IN_SHIFT_OUT (1 << 26) +#define FM10K_SW_SCAN_DATA_IN_UPDATE_NODES (1 << 27) +#define FM10K_SW_SCAN_DATA_IN_INJECT (1 << 28) +#define FM10K_SW_SCAN_DATA_IN_DRAIN (1 << 29) +#define FM10K_SW_SCAN_DATA_IN_PASSTHRU (1 << 30) +#define FM10K_SW_SCAN_DATA_IN_SINGLE (1 << 31) +#define FM10K_SW_CRM_DATA(m_, n_) \ + FM10K_SW_MGMT_REG(0x1000 + 0x2 * (m_) + (n_)) +#define FM10K_SW_CRM_CTRL FM10K_SW_MGMT_REG(0x2000) +#define FM10K_SW_CRM_STATUS FM10K_SW_MGMT_REG(0x2001) +#define FM10K_SW_CRM_TIME FM10K_SW_MGMT_REG(0x2002) +#define FM10K_SW_CRM_SRAM_CTRL FM10K_SW_MGMT_REG(0x2004) +#define FM10K_SW_CRM_IP FM10K_SW_MGMT_REG(0x2008) +#define FM10K_SW_CRM_IM FM10K_SW_MGMT_REG(0x200C) +#define FM10K_SW_CRM_COMMAND(n_) FM10K_SW_MGMT_REG(0x2080 + 0x2 * (n_)) +#define FM10K_SW_CRM_REGISTER(n_) FM10K_SW_MGMT_REG(0x2100 + 0x2 * (n_)) +#define FM10K_SW_CRM_PERIOD(n_) FM10K_SW_MGMT_REG(0x2180 + 0x2 * (n_)) +#define FM10K_SW_CRM_PARAM(n_) FM10K_SW_MGMT_REG(0x2200 + (n_)) +#define FM10K_SW_PLL_PCIE_CTRL FM10K_SW_MGMT_REG(0x2241) +#define FM10K_SW_PLL_PCIE_STAT FM10K_SW_MGMT_REG(0x2242) +#define FM10K_SW_SBUS_PCIE_CFG FM10K_SW_MGMT_REG(0x2243) +#define FM10K_SW_SBUS_PCIE_COMMAND FM10K_SW_MGMT_REG(0x2244) +#define FM10K_SW_SBUS_PCIE_REQUEST FM10K_SW_MGMT_REG(0x2245) +#define FM10K_SW_SBUS_PCIE_RESPONSE FM10K_SW_MGMT_REG(0x2246) +#define FM10K_SW_SBUS_PCIE_SPICO_IN FM10K_SW_MGMT_REG(0x2247) +#define FM10K_SW_SBUS_PCIE_SPICO_OUT FM10K_SW_MGMT_REG(0x2248) +#define FM10K_SW_SBUS_PCIE_IP FM10K_SW_MGMT_REG(0x2249) +#define FM10K_SW_SBUS_PCIE_IM FM10K_SW_MGMT_REG(0x224A) +#define FM10K_SW_MGMT_SYSTIME_CFG FM10K_SW_MGMT_REG(0x224C) +#define FM10K_SW_MGMT_SYSTIME FM10K_SW_MGMT_REG(0x224E) +#define FM10K_SW_MGMT_SYSTIME0 FM10K_SW_MGMT_REG(0x2250) +#define FM10K_SW_SYSTIME_PULSE_(n_) FM10K_SW_MGMT_REG(0x2252 + (n_)) +#define FM10K_SW_SYSTIME_CAPTURE_LO(n_) FM10K_SW_MGMT_REG(0x2258 + 0x2 * (n_)) +#define FM10K_SW_SYSTIME_CAPTURE_HI(n_) \ + FM10K_SW_MGMT_REG(0x2258 + 0x2 * (n_) + 0x1) +#define FM10K_SW_PCIE_XPLL_CTRL FM10K_SW_MGMT_REG(0x3000) +#define FM10K_SW_PCIE_CLK_CTRL FM10K_SW_MGMT_REG(0x3001) +#define FM10K_SW_PCIE_CLK_CTRL2 FM10K_SW_MGMT_REG(0x3002) +#define FM10K_SW_PCIE_CLKMON_RATIO_CFG FM10K_SW_MGMT_REG(0x3003) +#define FM10K_SW_PCIE_CLKMON_TOLERANCE_CFG FM10K_SW_MGMT_REG(0x3004) +#define FM10K_SW_PCIE_CLKMON_DEADLINES_CFG FM10K_SW_MGMT_REG(0x3005) +#define FM10K_SW_PCIE_CLK_STAT FM10K_SW_MGMT_REG(0x3006) +#define FM10K_SW_PCIE_CLK_IP FM10K_SW_MGMT_REG(0x3007) +#define FM10K_SW_PCIE_CLK_IM FM10K_SW_MGMT_REG(0x3008) +#define FM10K_SW_PCIE_WARM_RESET_DELAY FM10K_SW_MGMT_REG(0x3009) +#define FM10K_SW_EPL_BASE FM10K_SW_REG_OFF(0x0E0000) +#define FM10K_SW_EPL_PORT_REG(p_, r_) \ + (FM10K_SW_EPL_BASE + FM10K_SW_REG_OFF(0x400 * (p_) + (r_))) +#define FM10K_SW_EPL_LANE_REG(p_, l_, r_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x80 * (l_) + (r_)) + +/* EPL enumerated types + */ +#define FM10K_SW_EPL_QPL_MODE_XX_XX_XX_XX 0 +#define FM10K_SW_EPL_QPL_MODE_L1_L1_L1_L1 1 +#define FM10K_SW_EPL_QPL_MODE_XX_XX_XX_L4 2 +#define FM10K_SW_EPL_QPL_MODE_XX_XX_L4_XX 3 +#define FM10K_SW_EPL_QPL_MODE_XX_L4_XX_XX 4 +#define FM10K_SW_EPL_QPL_MODE_L4_XX_XX_XX 5 +#define FM10K_SW_EPL_PCS_SEL_DISABLE 0 +#define FM10K_SW_EPL_PCS_SEL_AN_73 1 +#define FM10K_SW_EPL_PCS_SEL_SGMII_10 2 +#define FM10K_SW_EPL_PCS_SEL_SGMII_100 3 +#define FM10K_SW_EPL_PCS_SEL_SGMII_1000 4 +#define FM10K_SW_EPL_PCS_SEL_1000BASEX 5 +#define FM10K_SW_EPL_PCS_SEL_10GBASER 6 +#define FM10K_SW_EPL_PCS_SEL_40GBASER 7 +#define FM10K_SW_EPL_PCS_SEL_100GBASER 8 + +#define FM10K_SW_LANE_OVERRIDE_NORMAL 0 +#define FM10K_SW_LANE_OVERRIDE_FORCE_GOOD 1 +#define FM10K_SW_LANE_OVERRIDE_FORCE_BAD 2 + +#define FM10K_SW_TX_MAX_FCS_MODE_PASSTHRU 0 +#define FM10K_SW_TX_MAX_FCS_MODE_PASSSTHRU_CHECK 1 +#define FM10K_SW_TX_MAX_FCS_MODE_REPLACE_GOOD 2 +#define FM10K_SW_TX_MAX_FCS_MODE_REPLACE_BAD 3 +#define FM10K_SW_TX_MAX_FCS_MODE_REPLACE_NORMAL 4 + +#define FM10K_SW_TX_MAC_DRAIN_MODE_DRAIN_DRAIN 0 +#define FM10K_SW_TX_MAC_DRAIN_MODE_DRAIN_NORMAL 1 +#define FM10K_SW_TX_MAC_DRAIN_MODE_HOLD_NORMAL 2 +#define FM10K_SW_TX_MAC_DRAIN_MODE_HOLD_HOLD 3 + +#define FM10K_SW_TX_MAC_FAULT_MODE_NORMAL 0 +#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_IDLE 1 +#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_LOCAL_FAULT 2 +#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_REMOTE_FAULT 3 +#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_LINK_INTERRUPTION 4 +#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_OK 5 +#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_ERROR 6 +#define FM10K_SW_TX_MAC_FAULT_MODE_FORCE_USER_VAL 7 + +#define FM10K_SW_EPL_IP(p_) FM10K_SW_EPL_PORT_REG((p_), 0x300) +#define FM10K_SW_EPL_IP_AN_PORT_INTERRUPT_lsb 0 +#define FM10K_SW_EPL_IP_AN_PORT_INTERRUPT_msb 3 +#define FM10K_SW_EPL_IP_AN_PORT_INTERRUPT(n_) (1 << ((n_) + 0)) +#define FM10K_SW_EPL_IP_LINK_PORT_INTERRUPT_lsb 4 +#define FM10K_SW_EPL_IP_LINK_PORT_INTERRUPT_msb 7 +#define FM10K_SW_EPL_IP_LINK_PORT_INTERRUPT(n_) (1 << ((n_) + 4)) +#define FM10K_SW_EPL_IP_SERDES_INTERRUPT_lsb 8 +#define FM10K_SW_EPL_IP_SERDES_INTERRUPT_msb 11 +#define FM10K_SW_EPL_IP_SERDES_INTERRUPT(n_) (1 << ((n_) + 8)) +#define FM10K_SW_EPL_IP_ERROR_INTERRUPT (1 << 12) +#define FM10K_SW_EPL_ERROR_IP(p_) FM10K_SW_EPL_PORT_REG((p_), 0x301) +#define FM10K_SW_EPL_ERROR_IM(p_) FM10K_SW_EPL_PORT_REG((p_), 0x302) +#define FM10K_SW_EPL_ERROR_IM_ALL FM10K_SW_MASK32(8, 0) +#define FM10K_SW_EPL_BIST_STATUS(p_) FM10K_SW_EPL_PORT_REG((p_), 0x303) +#define FM10K_SW_EPL_CFG_A(p_) FM10K_SW_EPL_PORT_REG((p_), 0x304) +#define FM10K_SW_EPL_CFG_A_SPEED_UP (1 << 0) +#define FM10K_SW_EPL_CFG_A_TIMEOUT_lsb 1 +#define FM10K_SW_EPL_CFG_A_TIMEOUT_msb 6 +#define FM10K_SW_EPL_CFG_A_ACTIVE(p_) (1 << ((p_) + 7)) +#define FM10K_SW_EPL_CFG_A_ACTIVE_QUAD (0xf << 7) +#define FM10K_SW_EPL_CFG_A_SKEW_TOLERANCE_lsb 11 +#define FM10K_SW_EPL_CFG_A_SKEW_TOLERANCE_msb 16 +#define FM10K_SW_EPL_CFG_B(p_) FM10K_SW_EPL_PORT_REG((p_), 0x305) +#define FM10K_SW_EPL_CFG_B_PCS_SEL_lsb(p_) ((p_) * 4) +#define FM10K_SW_EPL_CFG_B_PCS_SEL_msb(p_) (((p_) * 4) + 3) +#define FM10K_SW_EPL_CFG_B_QPL_MODE_lsb 16 +#define FM10K_SW_EPL_CFG_B_QPL_MODE_msb 18 +#define FM10K_SW_EPL_LED_STATUS(p_) FM10K_SW_EPL_PORT_REG((p_), 0x306) +#define FM10K_SW_EPL_LED_STATUS_PORT_RESET(n_) (1 << ((n_) * 6 + 0)) +#define FM10K_SW_EPL_LED_STATUS_PORT_LINK_UP(n_) (1 << ((n_) * 6 + 1)) +#define FM10K_SW_EPL_LED_STATUS_PORT_LOCAL_FAULT(n_) \ + (1 << ((n_) * 6 + 2)) +#define FM10K_SW_EPL_LED_STATUS_PORT_REMOTE_FAULT(n_) \ + (1 << ((n_) * 6 + 3)) +#define FM10K_SW_EPL_LED_STATUS_PORT_TRANSMITTING(n_) \ + (1 << ((n_) * 6 + 4)) +#define FM10K_SW_EPL_LED_STATUS_PORT_RECEIVING(n_) \ + (1 << ((n_) * 6 + 5)) +#define FM10K_SW_EPL_FIFO_ERROR_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x307) +#define FM10K_SW_EPL_TX_FIFO_RD_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x308) +#define FM10K_SW_EPL_TX_FIFO_WR_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x309) +#define FM10K_SW_EPL_TX_FIFO_A_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x30A) +#define FM10K_SW_EPL_TX_FIFO_B_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x30B) +#define FM10K_SW_EPL_TX_FIFO_C_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x30C) +#define FM10K_SW_EPL_TX_FIFO_D_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x30D) +#define FM10K_SW_EPL_RX_FIFO_RD_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x30E) +#define FM10K_SW_EPL_RX_FIFO_WR_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x30F) +#define FM10K_SW_EPL_RX_FIFO_A_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x310) +#define FM10K_SW_EPL_RX_FIFO_B_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x311) +#define FM10K_SW_EPL_RX_FIFO_C_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x312) +#define FM10K_SW_EPL_RX_FIFO_D_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x313) +#define FM10K_SW_PCS_ML_BASER_CFG(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x314) +#define FM10K_SW_PCS_ML_BASER_RX_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x315) +#define FM10K_SW_PCS_100GBASER_BIP_0(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x317) +#define FM10K_SW_PCS_100GBASER_BIP_1(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x318) +#define FM10K_SW_PCS_100GBASER_BIP_2(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x319) +#define FM10K_SW_PCS_100GBASER_BIP_3(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x31A) +#define FM10K_SW_PCS_100GBASER_BIP_4(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x31B) +#define FM10K_SW_PCS_100GBASER_BIP_5(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x31C) +#define FM10K_SW_PCS_100GBASER_BIP_6(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x31D) +#define FM10K_SW_PCS_100GBASER_BIP_7(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x31E) +#define FM10K_SW_PCS_100GBASER_BIP_8(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x31F) +#define FM10K_SW_PCS_100GBASER_BIP_9(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x320) +#define FM10K_SW_PCS_100GBASER_BIP_10(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x321) +#define FM10K_SW_PCS_100GBASER_BIP_11(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x322) +#define FM10K_SW_PCS_100GBASER_BIP_12(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x323) +#define FM10K_SW_PCS_100GBASER_BIP_13(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x324) +#define FM10K_SW_PCS_100GBASER_BIP_14(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x325) +#define FM10K_SW_PCS_100GBASER_BIP_15(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x326) +#define FM10K_SW_PCS_100GBASER_BIP_16(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x327) +#define FM10K_SW_PCS_100GBASER_BIP_17(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x328) +#define FM10K_SW_PCS_100GBASER_BIP_18(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x329) +#define FM10K_SW_PCS_100GBASER_BIP_19(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x32A) +#define FM10K_SW_PCS_100GBASER_BLOCK_LOCK(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x32B) +#define FM10K_SW_PCS_100GBASER_AMPS_LOCK(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x32C) +#define FM10K_SW_RS_FEC_UNCORRECTED(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x33D) +#define FM10K_SW_RS_FEC_CFG(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x32E) +#define FM10K_SW_RS_FEC_STATUS(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x330) +#define FM10K_SW_EPL_SYSTIME(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x331) +#define FM10K_SW_EPL_SYSTIME0(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x332) +#define FM10K_SW_EPL_SYSTIME_CFG(p_) \ + FM10K_SW_EPL_PORT_REG((p_), 0x333) +#define FM10K_SW_PORT_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x0) +#define FM10K_SW_AN_IM(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x1) +#define FM10K_SW_AN_IM_ALL FM10K_SW_MASK32(18, 0) +#define FM10K_SW_LINK_IM(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0x2) +#define FM10K_SW_LINK_IM_ALL FM10K_SW_MASK32(29, 0) +#define FM10K_SW_AN_IP(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0x3) +#define FM10K_SW_LINK_IP(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0x4) +#define FM10K_SW_MP_CFG(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0x6) +#define FM10K_SW_AN_37_PAGE_RX(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0x8) +#define FM10K_SW_AN_73_PAGE_RX(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0xA) +#define FM10K_SW_LINK_RULES(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0xC) +#define FM10K_SW_LINK_RULES_FAULT_TIME_SCALE_UP_lsb 0 +#define FM10K_SW_LINK_RULES_FAULT_TIME_SCALE_UP_msb 3 +#define FM10K_SW_LINK_RULES_FAULT_TICKS_UP_lsb 4 +#define FM10K_SW_LINK_RULES_FAULT_TICKS_UP_msb 8 +#define FM10K_SW_LINK_RULES_FAULT_TIME_SCALE_DOWN_lsb 9 +#define FM10K_SW_LINK_RULES_FAULT_TIME_SCALE_DOWN_msb 12 +#define FM10K_SW_LINK_RULES_FAULT_TICKS_DOWN_lsb 13 +#define FM10K_SW_LINK_RULES_FAULT_TICKS_DOWN_msb 17 +#define FM10K_SW_LINK_RULES_HEARTBEAT_TIME_SCALE_lsb 18 +#define FM10K_SW_LINK_RULES_HEARTBEAT_TIME_SCALE_msb 21 +#define FM10K_SW_MAC_CFG(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0x10) +#define FM10K_SW_MAC_CFG_ARRAY_SIZE 8 +#define FM10K_SW_MAC_CFG_TX_ANTI_BUBBLE_WATERMARK_lsb 0 +#define FM10K_SW_MAC_CFG_TX_ANTI_BUBBLE_WATERMARK_msb 5 +#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_WATERMARK_lsb 6 +#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_WATERMARK_msb 9 +#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_FAST_INC_lsb 10 +#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_FAST_INC_msb 17 +#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_SLOW_INC_lsb 18 +#define FM10K_SW_MAC_CFG_TX_RATE_FIFO_SLOW_INC_msb 25 +#define FM10K_SW_MAC_CFG_TX_IDLE_MIN_IFG_BYTES_lsb 26 +#define FM10K_SW_MAC_CFG_TX_IDLE_MIN_IFG_BYTES_msb 31 +#define FM10K_SW_MAC_CFG_TX_CLOCK_COMPENSATION_TIMEOUT_lsb 32 +#define FM10K_SW_MAC_CFG_TX_CLOCK_COMPENSATION_TIMEOUT_msb 47 +#define FM10K_SW_MAC_CFG_TX_CLOCK_COMPENSATION_ENABLE_bit 48 +#define FM10K_SW_MAC_CFG_TX_FAULT_MODE_lsb 49 +#define FM10K_SW_MAC_CFG_TX_FAULT_MODE_msb 51 +#define FM10K_SW_MAC_CFG_TX_PC_ACT_TIME_SCALE_lsb 52 +#define FM10K_SW_MAC_CFG_TX_PC_ACT_TIME_SCALE_msb 55 +#define FM10K_SW_MAC_CFG_TX_PC_ACT_TIMEOUT_lsb 56 +#define FM10K_SW_MAC_CFG_TX_PC_ACT_TIMEOUT_msb 63 +#define FM10K_SW_MAC_CFG_TX_DRAIN_MODE_lsb 64 +#define FM10K_SW_MAC_CFG_TX_DRAIN_MODE_msb 65 +#define FM10K_SW_MAC_CFG_TX_MIN_COLUMNS_lsb 66 +#define FM10K_SW_MAC_CFG_TX_MIN_COLUMNS_msb 71 +#define FM10K_SW_MAC_CFG_TX_SEG_MIN_SPACING_lsb 72 +#define FM10K_SW_MAC_CFG_TX_SEG_MIN_SPACING_msb 83 +#define FM10K_SW_MAC_CFG_TX_SEG_MAX_CREDIT_lsb 84 +#define FM10K_SW_MAC_CFG_TX_SEG_MAX_CREDIT_msb 95 +#define FM10K_SW_MAC_CFG_TX_SEG_SIZE_lsb 96 +#define FM10K_SW_MAC_CFG_TX_SEG_SIZE_msb 107 +#define FM10K_SW_MAC_CFG_TX_LP_IDLE_REQUEST_bit 108 +#define FM10K_SW_MAC_CFG_TX_LPI_AUTOMATIC_bit 109 +#define FM10K_SW_MAC_CFG_TX_LPI_TIMEOUT_lsb 110 +#define FM10K_SW_MAC_CFG_TX_LPI_TIMEOUT_msb 117 +#define FM10K_SW_MAC_CFG_TX_LPI_TIME_SCALE_lsb 118 +#define FM10K_SW_MAC_CFG_TX_LPI_TIME_SCALE_msb 119 +#define FM10K_SW_MAC_CFG_TX_LPI_HOLD_TIMEOUT_lsb 120 +#define FM10K_SW_MAC_CFG_TX_LPI_HOLD_TIMEOUT_msb 127 +#define FM10K_SW_MAC_CFG_TX_LPI_HOLD_TIME_SCALE_lsb 128 +#define FM10K_SW_MAC_CFG_TX_LPI_HOLD_TIME_SCALE_msb 129 +#define FM10K_SW_MAC_CFG_TX_FCS_MODE_lsb 130 +#define FM10K_SW_MAC_CFG_TX_FCS_MODE_msb 132 +#define FM10K_SW_MAC_CFG_TX_OBEY_LINT_bit 133 +#define FM10K_SW_MAC_CFG_TX_IDLE_ENABLE_DIC_bit 134 +#define FM10K_SW_MAC_CFG_CJPAT_ENABLE_bit 135 +#define FM10K_SW_MAC_CFG_RX_MIN_FRAME_LENGTH_lsb 136 +#define FM10K_SW_MAC_CFG_RX_MIN_FRAME_LENGTH_msb 143 +#define FM10K_SW_MAC_CFG_RX_MAX_FRAME_LENGTH_lsb 144 +#define FM10K_SW_MAC_CFG_RX_MAX_FRAME_LENGTH_msb 159 +#define FM10K_SW_MAC_CFG_START_CHAR_D_lsb 160 +#define FM10K_SW_MAC_CFG_START_CHAR_D_msb 167 +#define FM10K_SW_MAC_CFG_IEEE_1588_ENABLE_bit 168 +#define FM10K_SW_MAC_CFG_FCS_START_bit 169 +#define FM10K_SW_MAC_CFG_PREAMBLE_MODE_bit 170 +#define FM10K_SW_MAC_CFG_COUNTER_WRAP_bit 171 +#define FM10K_SW_MAC_CFG_LINK_FAULT_DISABLE_bit 172 +#define FM10K_SW_MAC_CFG_RX_DRAIN_bit 173 +#define FM10K_SW_MAC_CFG_RX_FCS_FORCE_BAD_bit 174 +#define FM10K_SW_MAC_CFG_RX_IGNORE_CODE_ERRORS_bit 175 +#define FM10K_SW_MAC_CFG_RX_IGNORE_UNDERSIZE_ERRORS_bit 176 +#define FM10K_SW_MAC_CFG_RX_IGNORE_OVERSIZE_ERRORS_bit 177 +#define FM10K_SW_MAC_CFG_RX_IGNORE_FCS_ERRORS_bit 178 +#define FM10K_SW_MAC_CFG_RX_IGNORE_PREAMBLE_ERRORS_bit 179 +#define FM10K_SW_MAC_CFG_RX_IGNORE_IFG_ERRORS_bit 180 +#define FM10K_SW_MAC_CFG_ERR_WRITE_lsb 181 +#define FM10K_SW_MAC_CFG_ERR_WRITE_msb 182 +#define FM10K_SW_MAC_CFG_RX_MIN_EVENT_RATE_lsb 183 +#define FM10K_SW_MAC_CFG_RX_MIN_EVENT_RATE_msb 186 +#define FM10K_SW_MAC_CFG_RX_PC_REQUEST_lsb 187 +#define FM10K_SW_MAC_CFG_RX_PC_REQUEST_msb 191 +#define FM10K_SW_MAC_CFG_RX_PC_SEG_SIZE_lsb 192 +#define FM10K_SW_MAC_CFG_RX_PC_SEG_SIZE_msb 196 +#define FM10K_SW_TX_SEQUENCE(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0x1A) +#define FM10K_SW_RX_SEQUENCE(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0x1C) +#define FM10K_SW_MAC_1588_STATUS(p_, l_) FM10K_SW_EPL_LANE_REG((p_), (l_), 0x1E) +#define FM10K_SW_WAKE_ERROR_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x20) +#define FM10K_SW_MAC_OVERSIZE_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x21) +#define FM10K_SW_MAC_JABBER_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x22) +#define FM10K_SW_MAC_UNDERSIZE_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x23) +#define FM10K_SW_MAC_RUNT_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x24) +#define FM10K_SW_MAC_OVERRUN_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x25) +#define FM10K_SW_MAC_UNDERRUN_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x26) +#define FM10K_SW_MAC_CODE_ERROR_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x27) +#define FM10K_SW_EPL_TX_FRAME_ERROR_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x28) +#define FM10K_SW_MAC_LINK_COUNTER(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x29) +#define FM10K_SW_PCS_1000BASEX_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x2A) +#define FM10K_SW_PCS_1000BASEX_RX_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x2B) +#define FM10K_SW_PCS_1000BASEX_TX_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x2C) +#define FM10K_SW_PCS_10GBASER_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x2D) +#define FM10K_SW_PCS_10GBASER_RX_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x2E) +#define FM10K_SW_PCS_10GBASER_TX_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x2F) +#define FM10K_SW_AN_37_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x30) +#define FM10K_SW_AN_37_TIMER_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x34) +#define FM10K_SW_AN_37_BASE_PAGE_TX(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x6) +#define FM10K_SW_AN_37_BASE_PAGE_RX(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x8) +#define FM10K_SW_AN_37_NEXT_PAGE_TX(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x6) +#define FM10K_SW_AN_37_NEXT_PAGE_RX(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x8) +#define FM10K_SW_SGMII_AN_TIMER_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x34) +#define FM10K_SW_SGMII_AN_TX_CONFIG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x6) +#define FM10K_SW_SGMII_AN_TX_CONFIG_LOOPBACK(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x6) +#define FM10K_SW_SGMII_AN_RX_CONFIG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x8) +#define FM10K_SW_AN_37_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x32) +#define FM10K_SW_AN_73_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x33) +#define FM10K_SW_AN_73_TIMER_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x34) +#define FM10K_SW_AN_73_BASE_PAGE_TX(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x6) +#define FM10K_SW_AN_73_BASE_PAGE_RX(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0xA) +#define FM10K_SW_AN_73_NEXT_PAGE_TX(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x6) +#define FM10K_SW_AN_73_NEXT_PAGE_RX(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0xA) +#define FM10K_SW_AN_73_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x36) +#define FM10K_SW_AN_73_TX_LCW(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x38) +#define FM10K_SW_AN_73_RX_LCW(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x3A) +#define FM10K_SW_PCSL_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x3C) +#define FM10K_SW_PCSL_CFG_SLIP_TIME_lsb 0 +#define FM10K_SW_PCSL_CFG_SLIP_TIME_msb 7 +#define FM10K_SW_PCSL_CFG_RX_BIT_SLIP_ENABLE (1 << 8) +#define FM10K_SW_PCSL_CFG_RX_BIT_SLIP_INITIAL (1 << 9) +#define FM10K_SW_PCSL_CFG_RX_GB_NARROW (1 << 10) +#define FM10K_SW_PCSL_CFG_TX_GB_NARROW (1 << 11) +#define FM10K_SW_MP_EEE_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x40) +#define FM10K_SW_PCS_1000BASEX_EEE_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x40) +#define FM10K_SW_PCS_10GBASER_EEE_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x40) +#define FM10K_SW_MP_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x44) +#define FM10K_SW_PCS_40GBASER_RX_BIP_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x44) +#define FM10K_SW_PCS_10GBASER_RX_BER_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x44) +#define FM10K_SW_DISPARITY_ERROR_8B10B(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x44) +#define FM10K_SW_LANE_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x45) +#define FM10K_SW_LANE_SERDES_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x46) +#define FM10K_SW_LANE_ENERGY_DETECT_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x47) +#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_OVERRIDE_lsb 0 +#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_OVERRIDE_msb 1 +#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_MASK_RX_SIGNAL_OK (1 << 2) +#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_MASK_RX_RDY (1 << 3) +#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_MASK_RX_ACTIVITY (1 << 4) +#define FM10K_SW_LANE_ENERGY_DETECT_CFG_ED_MASK_ENERGY_DETECT (1 << 5) +#define FM10K_SW_LANE_ACTIVITY_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x48) +#define FM10K_SW_LANE_SIGNAL_DETECT_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x49) +#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_OVERRIDE_lsb 0 +#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_OVERRIDE_msb 1 +#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_MASK_RX_SIGNAL_OK (1 << 2) +#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_MASK_RX_RDY (1 << 3) +#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_MASK_RX_ACTIVITY (1 << 4) +#define FM10K_SW_LANE_SIGNAL_DETECT_CFG_SD_MASK_ENERGY_DETECT (1 << 5) +#define FM10K_SW_LANE_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x4A) +#define FM10K_SW_LANE_SERDES_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x4B) +#define FM10K_SW_LANE_SERDES_STATUS_ANALOG_TO_CORE_lsb 0 +#define FM10K_SW_LANE_SERDES_STATUS_ANALOG_TO_CORE_msb 7 +#define FM10K_SW_LANE_SERDES_STATUS_CORE_STATUS_lsb 8 +#define FM10K_SW_LANE_SERDES_STATUS_CORE_STATUS_msb 23 +#define FM10K_SW_LANE_SERDES_STATUS_RX_SIGNAL_OK (1 << 12) +#define FM10K_SW_LANE_SERDES_STATUS_RX_RDY (1 << 24) +#define FM10K_SW_LANE_SERDES_STATUS_TX_RDY (1 << 25) +#define FM10K_SW_LANE_SERDES_STATUS_RX_IDLE_DETECT (1 << 26) +#define FM10K_SW_LANE_SERDES_STATUS_RX_ACTIVITY (1 << 27) +#define FM10K_SW_SERDES_IM(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x4C) +#define FM10K_SW_SERDES_IM_CORE_STATUS_0 (1 << 0) +#define FM10K_SW_SERDES_IM_CORE_STATUS_1 (1 << 1) +#define FM10K_SW_SERDES_IM_CORE_STATUS_2 (1 << 2) +#define FM10K_SW_SERDES_IM_CORE_STATUS_3 (1 << 3) +#define FM10K_SW_SERDES_IM_CORE_STATUS_4 (1 << 4) +#define FM10K_SW_SERDES_IM_RX_SIGNAL_OK \ + FM10K_SW_SERDES_IM_CORE_STATUS_4 +#define FM10K_SW_SERDES_IM_CORE_STATUS_5 (1 << 5) +#define FM10K_SW_SERDES_IM_CORE_STATUS_6 (1 << 6) +#define FM10K_SW_SERDES_IM_CORE_STATUS_7 (1 << 7) +#define FM10K_SW_SERDES_IM_CORE_STATUS_8 (1 << 8) +#define FM10K_SW_SERDES_IM_CORE_STATUS_9 (1 << 9) +#define FM10K_SW_SERDES_IM_CORE_STATUS_10 (1 << 10) +#define FM10K_SW_SERDES_IM_CORE_STATUS_11 (1 << 11) +#define FM10K_SW_SERDES_IM_CORE_STATUS_12 (1 << 12) +#define FM10K_SW_SERDES_IM_CORE_STATUS_13 (1 << 13) +#define FM10K_SW_SERDES_IM_CORE_STATUS_14 (1 << 14) +#define FM10K_SW_SERDES_IM_CORE_STATUS_15 (1 << 15) +#define FM10K_SW_SERDES_IM_TX_RDY (1 << 16) +#define FM10K_SW_SERDES_IM_RX_ENERGY_DETECT (1 << 17) +#define FM10K_SW_SERDES_IM_RX_SIGNAL_DETECT (1 << 18) +#define FM10K_SW_SERDES_IM_RX_RDY (1 << 19) +#define FM10K_SW_SERDES_IM_RX_ACTIVITY (1 << 20) +#define FM10K_SW_SERDES_IM_RX_IDLE_DETECT (1 << 21) +#define FM10K_SW_SERDES_IM_SAI_COMPLETE (1 << 22) +#define FM10K_SW_SERDES_IM_SAI_REQUEST_ERROR (1 << 23) +#define FM10K_SW_SERDES_IM_TX_CDC_FIFO_U_ERR (1 << 24) +#define FM10K_SW_SERDES_IM_TX_CDC_FIFO_ERROR (1 << 25) +#define FM10K_SW_SERDES_IM_RX_CDC_FIFO_U_ERR (1 << 26) +#define FM10K_SW_SERDES_IM_RX_CDC_FIFO_ERROR (1 << 27) +#define FM10K_SW_SERDES_IM_SLIP_REQUEST (1 << 28) +#define FM10K_SW_SERDES_IM_ANALOG_IP (1 << 29) +#define FM10K_SW_SERDES_IM_ALL \ + FM10K_SW_MASK32(29, 0) +#define FM10K_SW_SERDES_IP(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x4D) +#define FM10K_SW_SERDES_IP_CORE_STATUS_0 (1 << 0) +#define FM10K_SW_SERDES_IP_CORE_STATUS_1 (1 << 1) +#define FM10K_SW_SERDES_IP_CORE_STATUS_2 (1 << 2) +#define FM10K_SW_SERDES_IP_CORE_STATUS_3 (1 << 3) +#define FM10K_SW_SERDES_IP_CORE_STATUS_4 (1 << 4) +#define FM10K_SW_SERDES_IP_RX_SIGNAL_OK \ + FM10K_SW_SERDES_IP_CORE_STATUS_4 +#define FM10K_SW_SERDES_IP_CORE_STATUS_5 (1 << 5) +#define FM10K_SW_SERDES_IP_CORE_STATUS_6 (1 << 6) +#define FM10K_SW_SERDES_IP_CORE_STATUS_7 (1 << 7) +#define FM10K_SW_SERDES_IP_CORE_STATUS_8 (1 << 8) +#define FM10K_SW_SERDES_IP_CORE_STATUS_9 (1 << 9) +#define FM10K_SW_SERDES_IP_CORE_STATUS_10 (1 << 10) +#define FM10K_SW_SERDES_IP_CORE_STATUS_11 (1 << 11) +#define FM10K_SW_SERDES_IP_CORE_STATUS_12 (1 << 12) +#define FM10K_SW_SERDES_IP_CORE_STATUS_13 (1 << 13) +#define FM10K_SW_SERDES_IP_CORE_STATUS_14 (1 << 14) +#define FM10K_SW_SERDES_IP_CORE_STATUS_15 (1 << 15) +#define FM10K_SW_SERDES_IP_TX_RDY (1 << 16) +#define FM10K_SW_SERDES_IP_RX_ENERGY_DETECT (1 << 17) +#define FM10K_SW_SERDES_IP_RX_SIGNAL_DETECT (1 << 18) +#define FM10K_SW_SERDES_IP_RX_RDY (1 << 19) +#define FM10K_SW_SERDES_IP_RX_ACTIVITY (1 << 20) +#define FM10K_SW_SERDES_IP_RX_IDLE_DETECT (1 << 21) +#define FM10K_SW_SERDES_IP_SAI_COMPLETE (1 << 22) +#define FM10K_SW_SERDES_IP_SAI_REQUEST_ERROR (1 << 23) +#define FM10K_SW_SERDES_IP_TX_CDC_FIFO_U_ERR (1 << 24) +#define FM10K_SW_SERDES_IP_TX_CDC_FIFO_ERROR (1 << 25) +#define FM10K_SW_SERDES_IP_RX_CDC_FIFO_U_ERR (1 << 26) +#define FM10K_SW_SERDES_IP_RX_CDC_FIFO_ERROR (1 << 27) +#define FM10K_SW_SERDES_IP_SLIP_REQUEST (1 << 28) +#define FM10K_SW_SERDES_IP_ANALOG_IP (1 << 29) +#define FM10K_SW_SERDES_IP_ALL \ + FM10K_SW_MASK32(29, 0) +#define FM10K_SW_LANE_ANALOG_IM(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x4E) +#define FM10K_SW_LANE_ANALOG_IP(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x4F) +#define FM10K_SW_LANE_SAI_CFG(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x50) +#define FM10K_SW_LANE_SAI_CFG_CODE_lsb64 0 +#define FM10K_SW_LANE_SAI_CFG_CODE_msb64 15 +#define FM10K_SW_LANE_SAI_CFG_DATA_lsb64 16 +#define FM10K_SW_LANE_SAI_CFG_DATA_msb64 31 +#define FM10K_SW_LANE_SAI_CFG_RESULT_PATTERN_lsb64 32 +#define FM10K_SW_LANE_SAI_CFG_RESULT_PATTERN_msb64 47 +#define FM10K_SW_LANE_SAI_CFG_RESULT_MODE_lsb64 48 +#define FM10K_SW_LANE_SAI_CFG_RESULT_MODE_msb64 49 +#define FM10K_SW_LANE_SAI_CFG_REQUEST (1ULL << 50) +#define FM10K_SW_LANE_SAI_STATUS(p_, l_) \ + FM10K_SW_EPL_LANE_REG((p_), (l_), 0x52) +#define FM10K_SW_LANE_SAI_STATUS_RESULT_lsb 0 +#define FM10K_SW_LANE_SAI_STATUS_RESULT_msb 15 +#define FM10K_SW_LANE_SAI_STATUS_COMPLETE (1 << 16) +#define FM10K_SW_LANE_SAI_STATUS_ACCESS_REQUEST (1 << 17) +#define FM10K_SW_LANE_SAI_STATUS_IN_PROGRESS (1 << 18) +#define FM10K_SW_LANE_SAI_STATUS_BUSY (1 << 19) +#define FM10K_SW_LANE_SAI_STATUS_REQUEST_ERROR (1 << 20) + +#define FM10K_SW_PORTS_MGMT_BASE FM10K_SW_REG_OFF(0x0E8000) +#define FM10K_SW_PORTS_MGMT_REG(wo_) \ + (FM10K_SW_PORTS_MGMT_BASE + FM10K_SW_REG_OFF(wo_)) + +#define FM10K_SW_PLL_EPL_CTRL FM10K_SW_PORTS_MGMT_REG(0x0) +#define FM10K_SW_PLL_EPL_STAT FM10K_SW_PORTS_MGMT_REG(0x1) +#define FM10K_SW_PLL_FABRIC_CTRL FM10K_SW_PORTS_MGMT_REG(0x2) +#define FM10K_SW_PLL_FABRIC_REFDIV_lsb 3 +#define FM10K_SW_PLL_FABRIC_REFDIV_msb 8 +#define FM10K_SW_PLL_FABRIC_FBDIV4_lsb 9 +#define FM10K_SW_PLL_FABRIC_FBDIV4_msb 9 +#define FM10K_SW_PLL_FABRIC_FBDIV255_lsb 10 +#define FM10K_SW_PLL_FABRIC_FBDIV255_msb 17 +#define FM10K_SW_PLL_FABRIC_OUTDIV_lsb 18 +#define FM10K_SW_PLL_FABRIC_OUTDIV_msb 23 +#define FM10K_SW_PLL_FABRIC_STAT FM10K_SW_PORTS_MGMT_REG(0x3) +#define FM10K_SW_PLL_FABRIC_LOCK FM10K_SW_PORTS_MGMT_REG(0x4) +#define FM10K_SW_PLL_FABRIC_FREQSEL_lsb 4 +#define FM10K_SW_PLL_FABRIC_FREQSEL_msb 7 +#define FM10K_SW_PLL_FABRIC_FREQSEL_CTRL 0 +#define FM10K_SW_PLL_FABRIC_FREQSEL_F600 1 +#define FM10K_SW_PLL_FABRIC_FREQSEL_F500 2 +#define FM10K_SW_PLL_FABRIC_FREQSEL_F400 3 +#define FM10K_SW_PLL_FABRIC_FREQSEL_F300 4 +#define FM10K_SW_SBUS_EPL_CFG FM10K_SW_PORTS_MGMT_REG(0x5) +#define FM10K_SW_SBUS_EPL_COMMAND FM10K_SW_PORTS_MGMT_REG(0x6) +#define FM10K_SW_SBUS_EPL_REQUEST FM10K_SW_PORTS_MGMT_REG(0x7) +#define FM10K_SW_SBUS_EPL_RESPONSE FM10K_SW_PORTS_MGMT_REG(0x8) +#define FM10K_SW_SBUS_EPL_SPICO_IN FM10K_SW_PORTS_MGMT_REG(0x9) +#define FM10K_SW_SBUS_EPL_SPICO_OUT FM10K_SW_PORTS_MGMT_REG(0xA) +#define FM10K_SW_SBUS_EPL_IP FM10K_SW_PORTS_MGMT_REG(0xB) +#define FM10K_SW_SBUS_EPL_IM FM10K_SW_PORTS_MGMT_REG(0xC) +#define FM10K_SW_ETHCLK_CFG(n_) FM10K_SW_PORTS_MGMT_REG(0xE + (n_)) +#define FM10K_SW_ETHCLK_RATIO(n_) FM10K_SW_PORTS_MGMT_REG(0x10 + (n_)) +#define FM10K_SW_PM_CLKOBS_CTRL FM10K_SW_PORTS_MGMT_REG(0x12) + +#define FM10K_SW_PCIE_CFG_BASE FM10K_SW_REG_OFF(0x120000) +#define FM10K_SW_PCIE_CFG_REG(wo_) \ + (FM10K_SW_PCIE_CFG_BASE + FM10K_SW_REG_OFF(wo_)) + +/* + * These register offsets can also be passed to fm10k_read_config(), which + * will mask off the upper bits + */ +#define FM10K_SW_PCIE_CFG_ID FM10K_SW_PCIE_CFG_REG(0x0) +#define FM10K_SW_PCIE_CFG_CMD FM10K_SW_PCIE_CFG_REG(0x1) +#define FM10K_SW_PCIE_CFG_1 FM10K_SW_PCIE_CFG_REG(0x2) +#define FM10K_SW_PCIE_CFG_2 FM10K_SW_PCIE_CFG_REG(0x3) +#define FM10K_SW_PCIE_CFG_BAR0 FM10K_SW_PCIE_CFG_REG(0x4) +#define FM10K_SW_PCIE_CFG_BAR1 FM10K_SW_PCIE_CFG_REG(0x5) +#define FM10K_SW_PCIE_CFG_BAR2 FM10K_SW_PCIE_CFG_REG(0x6) +#define FM10K_SW_PCIE_CFG_BAR3 FM10K_SW_PCIE_CFG_REG(0x7) +#define FM10K_SW_PCIE_CFG_BAR4 FM10K_SW_PCIE_CFG_REG(0x8) +#define FM10K_SW_PCIE_CFG_BAR5 FM10K_SW_PCIE_CFG_REG(0x9) +#define FM10K_SW_PCIE_CFG_CARDBUS FM10K_SW_PCIE_CFG_REG(0xA) +#define FM10K_SW_PCIE_CFG_SUBID FM10K_SW_PCIE_CFG_REG(0xB) +#define FM10K_SW_PCIE_CFG_EXP_ROM FM10K_SW_PCIE_CFG_REG(0xC) +#define FM10K_SW_PCIE_CFG_CAP_PTR FM10K_SW_PCIE_CFG_REG(0xD) +#define FM10K_SW_PCIE_CFG_RSVD FM10K_SW_PCIE_CFG_REG(0xE) +#define FM10K_SW_PCIE_CFG_INT FM10K_SW_PCIE_CFG_REG(0xF) +#define FM10K_SW_PCIE_CFG_PM_CAP FM10K_SW_PCIE_CFG_REG(0x10) +#define FM10K_SW_PCIE_CFG_PM_CTRL FM10K_SW_PCIE_CFG_REG(0x11) +#define FM10K_SW_PCIE_CFG_PCIE_CAP FM10K_SW_PCIE_CFG_REG(0x1C) +#define FM10K_SW_PCIE_CFG_PCIE_DEV_CAP FM10K_SW_PCIE_CFG_REG(0x1D) +#define FM10K_SW_PCIE_CFG_PCIE_DEV_CTRL FM10K_SW_PCIE_CFG_REG(0x1E) +#define FM10K_SW_PCIE_CFG_PCIE_LINK_CAP FM10K_SW_PCIE_CFG_REG(0x1F) +#define FM10K_SW_PCIE_CFG_PCIE_LINK_CTRL FM10K_SW_PCIE_CFG_REG(0x20) +#define FM10K_SW_PCIE_CFG_LINK_SPEED_lsb 16 +#define FM10K_SW_PCIE_CFG_LINK_SPEED_msb 19 +#define FM10K_SW_PCIE_CFG_LINK_SPEED_2P5 1 +#define FM10K_SW_PCIE_CFG_LINK_SPEED_5 2 +#define FM10K_SW_PCIE_CFG_LINK_SPEED_8 3 +#define FM10K_SW_PCIE_CFG_LINK_WIDTH_lsb 20 +#define FM10K_SW_PCIE_CFG_LINK_WIDTH_msb 24 +#define FM10K_SW_PCIE_CFG_PCIE_DEV_CAP2 FM10K_SW_PCIE_CFG_REG(0x25) +#define FM10K_SW_PCIE_CFG_PCIE_DEV_CTRL2 FM10K_SW_PCIE_CFG_REG(0x26) +#define FM10K_SW_PCIE_CFG_PCIE_LINK_CTRL2 FM10K_SW_PCIE_CFG_REG(0x28) +#define FM10K_SW_PCIE_CFG_MSIX_CAP FM10K_SW_PCIE_CFG_REG(0x2C) +#define FM10K_SW_PCIE_CFG_MSIX_TABLE_OFFSET FM10K_SW_PCIE_CFG_REG(0x2D) +#define FM10K_SW_PCIE_CFG_MSIX_PBA FM10K_SW_PCIE_CFG_REG(0x2E) +#define FM10K_SW_PCIE_CFG_VPD_CAP FM10K_SW_PCIE_CFG_REG(0x34) +#define FM10K_SW_PCIE_CFG_VPD_DATA FM10K_SW_PCIE_CFG_REG(0x35) +#define FM10K_SW_PCIE_CFG_AER_HDR FM10K_SW_PCIE_CFG_REG(0x40) +#define FM10K_SW_PCIE_CFG_AER_UNERR_STATUS FM10K_SW_PCIE_CFG_REG(0x41) +#define FM10K_SW_PCIE_CFG_AER_UNERR_MASK FM10K_SW_PCIE_CFG_REG(0x42) +#define FM10K_SW_PCIE_CFG_AER_UNERR_SEVERITY FM10K_SW_PCIE_CFG_REG(0x43) +#define FM10K_SW_PCIE_CFG_AER_COERR_STATUS FM10K_SW_PCIE_CFG_REG(0x44) +#define FM10K_SW_PCIE_CFG_AER_COERR_MASK FM10K_SW_PCIE_CFG_REG(0x45) +#define FM10K_SW_PCIE_CFG_AER_CTRL FM10K_SW_PCIE_CFG_REG(0x46) +#define FM10K_SW_PCIE_CFG_AER_HEADER_LOG0 FM10K_SW_PCIE_CFG_REG(0x47) +#define FM10K_SW_PCIE_CFG_AER_HEADER_LOG1 FM10K_SW_PCIE_CFG_REG(0x48) +#define FM10K_SW_PCIE_CFG_AER_HEADER_LOG2 FM10K_SW_PCIE_CFG_REG(0x49) +#define FM10K_SW_PCIE_CFG_AER_HEADER_LOG3 FM10K_SW_PCIE_CFG_REG(0x4A) +#define FM10K_SW_PCIE_CFG_SPD_HDR FM10K_SW_PCIE_CFG_REG(0x52) +#define FM10K_SW_PCIE_CFG_SPD_NUMBER_L FM10K_SW_PCIE_CFG_REG(0x53) +#define FM10K_SW_PCIE_CFG_SPD_NUMBER_H FM10K_SW_PCIE_CFG_REG(0x54) +#define FM10K_SW_PCIE_CFG_ARI_HDR FM10K_SW_PCIE_CFG_REG(0x56) +#define FM10K_SW_PCIE_CFG_ARI_CTRL FM10K_SW_PCIE_CFG_REG(0x57) +#define FM10K_SW_PCIE_CFG_SPCIE_HDR FM10K_SW_PCIE_CFG_REG(0x5A) +#define FM10K_SW_PCIE_CFG_SPCIE_LINK_CTRL3 FM10K_SW_PCIE_CFG_REG(0x5B) +#define FM10K_SW_PCIE_CFG_SPCIE_ERR_STS FM10K_SW_PCIE_CFG_REG(0x5C) +#define FM10K_SW_PCIE_CFG_SPCIE_LINK_EQ01 FM10K_SW_PCIE_CFG_REG(0x5D) +#define FM10K_SW_PCIE_CFG_SPCIE_LINK_EQ23 FM10K_SW_PCIE_CFG_REG(0x5E) +#define FM10K_SW_PCIE_CFG_SPCIE_LINK_EQ45 FM10K_SW_PCIE_CFG_REG(0x5F) +#define FM10K_SW_PCIE_CFG_SPCIE_LINK_EQ67 FM10K_SW_PCIE_CFG_REG(0x60) +#define FM10K_SW_PCIE_CFG_SRIOV_HDR FM10K_SW_PCIE_CFG_REG(0x62) +#define FM10K_SW_PCIE_CFG_SRIOV_CAP FM10K_SW_PCIE_CFG_REG(0x63) +#define FM10K_SW_PCIE_CFG_SRIOV_CTRL FM10K_SW_PCIE_CFG_REG(0x64) +#define FM10K_SW_PCIE_CFG_SRIOV_CFG FM10K_SW_PCIE_CFG_REG(0x65) +#define FM10K_SW_PCIE_CFG_SRIOV_NUM FM10K_SW_PCIE_CFG_REG(0x66) +#define FM10K_SW_PCIE_CFG_SRIOV_MAP FM10K_SW_PCIE_CFG_REG(0x67) +#define FM10K_SW_PCIE_CFG_SRIOV_DEVID FM10K_SW_PCIE_CFG_REG(0x69) +#define FM10K_SW_PCIE_CFG_SRIOV_PAGE_SUP FM10K_SW_PCIE_CFG_REG(0x69) +#define FM10K_SW_PCIE_CFG_SRIOV_PAGE_CFG FM10K_SW_PCIE_CFG_REG(0x6A) +#define FM10K_SW_PCIE_CFG_SRIOV_BAR0 FM10K_SW_PCIE_CFG_REG(0x6B) +#define FM10K_SW_PCIE_CFG_SRIOV_BAR1 FM10K_SW_PCIE_CFG_REG(0x6C) +#define FM10K_SW_PCIE_CFG_SRIOV_BAR2 FM10K_SW_PCIE_CFG_REG(0x6D) +#define FM10K_SW_PCIE_CFG_SRIOV_BAR3 FM10K_SW_PCIE_CFG_REG(0x6E) +#define FM10K_SW_PCIE_CFG_SRIOV_BAR4 FM10K_SW_PCIE_CFG_REG(0x6F) +#define FM10K_SW_PCIE_CFG_SRIOV_BAR5 FM10K_SW_PCIE_CFG_REG(0x70) +#define FM10K_SW_PCIE_CFG_SRIOV_MIG FM10K_SW_PCIE_CFG_REG(0x71) +#define FM10K_SW_PCIE_CFG_TPH_HDR FM10K_SW_PCIE_CFG_REG(0x72) +#define FM10K_SW_PCIE_CFG_TPH_CAP FM10K_SW_PCIE_CFG_REG(0x73) +#define FM10K_SW_PCIE_CFG_TPH_CTRL FM10K_SW_PCIE_CFG_REG(0x74) +#define FM10K_SW_PCIE_CFG_ACS_HDR FM10K_SW_PCIE_CFG_REG(0x76) +#define FM10K_SW_PCIE_CFG_ACS_CAP FM10K_SW_PCIE_CFG_REG(0x77) +#define FM10K_SW_PCIE_PORTLOGIC FM10K_SW_PCIE_CFG_REG(0x1C0) +#define FM10K_SW_PCIE_PORTLOGIC_LINK_STATE FM10K_SW_PCIE_CFG_REG(0x1CA) + + +#define FM10K_SW_FFU_BASE FM10K_SW_REG_OFF(0xC00000) +#define FM10K_SW_FFU_REG(wo_) (FM10K_SW_FFU_BASE + FM10K_SW_REG_OFF(wo_)) +#define FM10K_SW_FFU_NUM_SLICES 32 +#define FM10K_SW_FFU_NUM_SCENARIOS 32 + +/* FFU enumerated types */ +#define FM10K_SW_FFU_MUX_SEL_MAP_DIP_MAP_SIP 0 +#define FM10K_SW_FFU_MUX_SEL_MAP_DMAC_MAP_SMAC 1 +#define FM10K_SW_FFU_MUX_SEL_MAP_PROT_MAP_LENGTH 2 +#define FM10K_SW_FFU_MUX_SEL_MAP_SRC_MAP_TYPE 3 +#define FM10K_SW_FFU_MUX_SEL_USER 4 +#define FM10K_SW_FFU_MUX_SEL_FTYPE_SWPRI 5 +#define FM10K_SW_FFU_MUX_SEL_IPMISC 6 +#define FM10K_SW_FFU_MUX_SEL_TOS 7 +#define FM10K_SW_FFU_MUX_SEL_PROT 8 +#define FM10K_SW_FFU_MUX_SEL_TTL 9 +#define FM10K_SW_FFU_MUX_SEL_SRC_PORT 10 +#define FM10K_SW_FFU_MUX_SEL_VPRI_VID_11_8 11 +#define FM10K_SW_FFU_MUX_SEL_VID_7_0 12 +#define FM10K_SW_FFU_MUX_SEL_RXTAG 13 +#define FM10K_SW_FFU_MUX_SEL_L2_DMAC_15_0 14 +#define FM10K_SW_FFU_MUX_SEL_L2_DMAC_31_16 15 +#define FM10K_SW_FFU_MUX_SEL_L2_DMAC_47_32 16 +#define FM10K_SW_FFU_MUX_SEL_L2_SMAC_15_0 17 +#define FM10K_SW_FFU_MUX_SEL_L2_SMAC_31_16 18 +#define FM10K_SW_FFU_MUX_SEL_L2_SMAC_47_32 19 +#define FM10K_SW_FFU_MUX_SEL_DGLORT 20 +#define FM10K_SW_FFU_MUX_SEL_SGLORT 21 +#define FM10K_SW_FFU_MUX_SEL_VPRI_VID 22 +#define FM10K_SW_FFU_MUX_SEL_VPRI2_VID2 23 +#define FM10K_SW_FFU_MUX_SEL_L2_TYPE 24 +#define FM10K_SW_FFU_MUX_SEL_L4_DST 25 +#define FM10K_SW_FFU_MUX_SEL_L4_SRC 26 +#define FM10K_SW_FFU_MUX_SEL_MAP_L4_DST 27 +#define FM10K_SW_FFU_MUX_SEL_MAP_L4_SRC 28 +#define FM10K_SW_FFU_MUX_SEL_L4A 29 +#define FM10K_SW_FFU_MUX_SEL_L4B 30 +#define FM10K_SW_FFU_MUX_SEL_L4C 31 +#define FM10K_SW_FFU_MUX_SEL_L4D 32 +#define FM10K_SW_FFU_MUX_SEL_MAP_VPRI1_VID1 33 +#define FM10K_SW_FFU_MUX_SEL_L3_DIP_31_0 34 +#define FM10K_SW_FFU_MUX_SEL_L3_DIP_63_32 35 +#define FM10K_SW_FFU_MUX_SEL_L3_DIP_95_64 36 +#define FM10K_SW_FFU_MUX_SEL_L3_DIP_127_96 37 +#define FM10K_SW_FFU_MUX_SEL_L3_SIP_31_0 38 +#define FM10K_SW_FFU_MUX_SEL_L3_SIP_63_32 39 +#define FM10K_SW_FFU_MUX_SEL_L3_SIP_95_64 40 +#define FM10K_SW_FFU_MUX_SEL_L3_SIP_127_96 41 + +#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_INDEX_lsb 0 +#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_INDEX_msb 15 +#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_COUNT_lsb 16 +#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_COUNT_msb 19 +#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_ARP_TYPE_EXP (1 << 20) + +#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_GLORT_DGLORT_lsb 0 +#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_GLORT_DGLORT_msb 15 +#define FM10K_SW_FFU_SLICE_SRAM_ROUTE_GLORT_FLOOD_SET (1 << 20) + +#define FM10K_SW_FFU_SLICE_SRAM_SET_BITS_BYTE_MASK_lsb 0 +#define FM10K_SW_FFU_SLICE_SRAM_SET_BITS_BYTE_MASK_msb 7 +#define FM10K_SW_FFU_SLICE_SRAM_SET_BITS_BYTE_DATA_lsb 8 +#define FM10K_SW_FFU_SLICE_SRAM_SET_BITS_BYTE_DATA_msb 15 +#define FM10K_SW_FFU_SLICE_SRAM_SET_BITS_SUB_CMD_lsb 16 +#define FM10K_SW_FFU_SLICE_SRAM_SET_BITS_SUB_CMD_msb 20 + +#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_VLAN_lsb 0 +#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_VLAN_msb 11 +#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_PRI_lsb 12 +#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_PRI_msb 15 +#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_TX_TAG_lsb 16 +#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_TX_TAG_msb 17 +#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_SET_VPRI (1 << 18) +#define FM10K_SW_FFU_SLICE_SRAM_SET_VLAN_SET_PRI (1 << 19) + +#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_DSCP_lsb 0 +#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_DSCP_msb 5 +#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_PRI_lsb 12 +#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_PRI_msb 15 +#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_SET_DSCP (1 << 17) +#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_SET_VPRI (1 << 18) +#define FM10K_SW_FFU_SLICE_SRAM_SET_PRI_SET_PRI (1 << 19) + +/* FFU Registers */ +#define FM10K_SW_FFU_SLICE_TCAM(sl_, n_) \ + FM10K_SW_FFU_REG(0x2000 * (sl_) + 0x4 * (n_)) +#define FM10K_SW_FFU_SLICE_TCAM_ENTRIES 1024 +#define FM10K_SW_FFU_SLICE_TCAM_KEY_lsb64 0 +#define FM10K_SW_FFU_SLICE_TCAM_KEY_msb64 31 +#define FM10K_SW_FFU_SLICE_TCAM_KEY_TOP_lsb64 32 +#define FM10K_SW_FFU_SLICE_TCAM_KEY_TOP_msb64 39 +#define FM10K_SW_FFU_SLICE_SRAM(sl_, n_) \ + FM10K_SW_FFU_REG(0x1000 + 0x2000 * (sl_) + 0x2 * (n_)) +#define FM10K_SW_FFU_SLICE_SRAM_COMMAND_lsb64 21 +#define FM10K_SW_FFU_SLICE_SRAM_COMMAND_msb64 22 +#define FM10K_SW_FFU_SLICE_SRAM_COMMAND_ROUTE_ARP 0 +#define FM10K_SW_FFU_SLICE_SRAM_COMMAND_ROUTE_GLORT 1 +#define FM10K_SW_FFU_SLICE_SRAM_COMMAND_BIT_SET 2 +#define FM10K_SW_FFU_SLICE_SRAM_COMMAND_FIELD_SET 3 +#define FM10K_SW_FFU_SLICE_SRAM_COUNTER_INDEX_lsb64 23 +#define FM10K_SW_FFU_SLICE_SRAM_COUNTER_INDEX_msb64 34 +#define FM10K_SW_FFU_SLICE_SRAM_COUNTER_BANK_lsb64 35 +#define FM10K_SW_FFU_SLICE_SRAM_COUNTER_BANK_msb64 36 +#define FM10K_SW_FFU_SLICE_SRAM_PRECEDENCE_lsb64 37 +#define FM10K_SW_FFU_SLICE_SRAM_PRECEDENCE_msb64 39 +#define FM10K_SW_FFU_SLICE_VALID(sl_) \ + FM10K_SW_FFU_REG(0x1800 + 0x2000 * (sl_)) +#define FM10K_SW_FFU_SLICE_VALID_SCENARIO(s_) (1ULL << (s_)) +#define FM10K_SW_FFU_SLICE_VALID_ALL_SCENARIOS FM10K_SW_MASK32(31, 0) +#define FM10K_SW_FFU_SLICE_CASCADE_ACTION(sl_) \ + FM10K_SW_FFU_REG(0x1804 + 0x2000 * (sl_)) +#define FM10K_SW_FFU_SLICE_CFG(sl_, scen_) \ + FM10K_SW_FFU_REG(0x1840 + 0x2 * (scen_) + 0x2000 * (sl_)) +#define FM10K_SW_FFU_SLICE_CFG_SELECT_0_lsb64 0 +#define FM10K_SW_FFU_SLICE_CFG_SELECT_0_msb64 5 +#define FM10K_SW_FFU_SLICE_CFG_SELECT_1_lsb64 6 +#define FM10K_SW_FFU_SLICE_CFG_SELECT_1_msb64 11 +#define FM10K_SW_FFU_SLICE_CFG_SELECT_2_lsb64 12 +#define FM10K_SW_FFU_SLICE_CFG_SELECT_2_msb64 17 +#define FM10K_SW_FFU_SLICE_CFG_SELECT_3_lsb64 18 +#define FM10K_SW_FFU_SLICE_CFG_SELECT_3_msb64 23 +#define FM10K_SW_FFU_SLICE_CFG_SELECT_TOP_lsb64 24 +#define FM10K_SW_FFU_SLICE_CFG_SELECT_TOP_msb64 29 +#define FM10K_SW_FFU_SLICE_CFG_START_COMPARE (1ULL << 30) +#define FM10K_SW_FFU_SLICE_CFG_START_ACTION (1ULL << 31) +#define FM10K_SW_FFU_SLICE_CFG_VALID_LOW (1ULL << 32) +#define FM10K_SW_FFU_SLICE_CFG_VALID_HIGH (1ULL << 33) +#define FM10K_SW_FFU_SLICE_CFG_CASE_lsb64 34 +#define FM10K_SW_FFU_SLICE_CFG_CASE_msb64 37 +#define FM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_lsb64 38 +#define FM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_msb64 39 +#define FM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_NOT_MAPPED 0 +#define FM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_TOP_LOW_NIBBLE 1 +#define FM10K_SW_FFU_SLICE_CFG_CASE_LOCATION_TOP_HIGH_NIBBLE 2 +#define FM10K_SW_FFU_MASTER_VALID FM10K_SW_FFU_REG(0x40000) +#define FM10K_SW_FFU_MASTER_VALID_SLICE_VALID(s_) (1ULL << (s_)) +#define FM10K_SW_FFU_MASTER_VALID_ALL_SLICES_VALID FM10K_SW_MASK64(31, 0) +#define FM10K_SW_FFU_MASTER_VALID_CHUNK_VALID(c_) (1ULL << ((c_) + 32)) +#define FM10K_SW_FFU_MASTER_VALID_ALL_CHUNKS_VALID FM10K_SW_MASK64(63, 32) + +#define FM10K_SW_L2LOOKUP_BASE FM10K_SW_REG_OFF(0xC80000) +#define FM10K_SW_L2LOOKUP_REG(wo_) \ + (FM10K_SW_L2LOOKUP_BASE + FM10K_SW_REG_OFF(wo_)) + +#define FM10K_SW_MA_TABLE(t_, n_) \ + FM10K_SW_L2LOOKUP_REG(0x10000 * (t_) + 0x4 * (n_)) +#define FM10K_SW_INGRESS_VID_TABLE(v_) \ + FM10K_SW_L2LOOKUP_REG(0x20000 + 0x4 * (v_)) +#define FM10K_SW_INGRESS_VID_TABLE_ENTRIES 4096 +#define FM10K_SW_INGRESS_VID_TABLE_MEMBERSHIP(l_) (1ULL << (l_)) + +/* note these bit positions are relative + * to the start of the upper 64-bit word + */ +#define FM10K_SW_INGRESS_VID_TABLE_FID_lsb64 (64 - 64) +#define FM10K_SW_INGRESS_VID_TABLE_FID_msb64 (75 - 64) +#define FM10K_SW_INGRESS_VID_TABLE_MST_INDEX_lsb64 (76 - 64) +#define FM10K_SW_INGRESS_VID_TABLE_MST_INDEX_msb64 (83 - 64) +#define FM10K_SW_INGRESS_VID_TABLE_COUNTER_INDEX_lsb64 (84 - 64) +#define FM10K_SW_INGRESS_VID_TABLE_COUNTER_INDEX_msb64 (89 - 64) +#define FM10K_SW_INGRESS_VID_TABLE_REFLECT (1ULL << (90 - 64)) +#define FM10K_SW_INGRESS_VID_TABLE_TRAP_IGMP (1ULL << (91 - 64)) +#define FM10K_SW_EGRESS_VID_TABLE(v_) \ + FM10K_SW_L2LOOKUP_REG(0x24000 + 0x4 * (v_)) +#define FM10K_SW_EGRESS_VID_TABLE_ENTRIES 4096 +#define FM10K_SW_EGRESS_VID_TABLE_MEMBERSHIP(l_) (1ULL << (l_)) + +/* note these bit positions are relative to + * the start of the upper 64-bit word + */ +#define FM10K_SW_EGRESS_VID_TABLE_FID_lsb64 (64 - 64) +#define FM10K_SW_EGRESS_VID_TABLE_FID_msb64 (75 - 64) +#define FM10K_SW_EGRESS_VID_TABLE_MST_INDEX_lsb64 (76 - 64) +#define FM10K_SW_EGRESS_VID_TABLE_MST_INDEX_msb64 (83 - 64) +#define FM10K_SW_EGRESS_VID_TABLE_MTU_INDEX_lsb64 (84 - 64) +#define FM10K_SW_EGRESS_VID_TABLE_MTU_INDEX_msb64 (86 - 64) +#define FM10K_SW_EGRESS_VID_TABLE_TRIG_ID_lsb64 (87 - 64) +#define FM10K_SW_EGRESS_VID_TABLE_TRIG_ID_msb64 (92 - 64) +#define FM10K_SW_MA_USED_TABLE(t_, n_) \ + FM10K_SW_L2LOOKUP_REG(0x28000 + 0x200 * (t_) + (n_)) +#define FM10K_SW_INGRESS_MST_TABLE(t_, n_) \ + FM10K_SW_L2LOOKUP_REG(0x28400 + 0x200 * (t_) + 0x2 * (n_)) +#define FM10K_SW_INGRESS_MST_TABLE_PORTS_PER_TABLE 24 +#define FM10K_SW_INGRESS_MST_TABLE_STP_STATE_lsb64(l_) \ + (((l_) % FM10K_SW_INGRESS_MST_TABLE_PORTS_PER_TABLE) * 2) +#define FM10K_SW_INGRESS_MST_TABLE_STP_STATE_msb64(l_) \ + (FM10K_SW_INGRESS_MST_TABLE_STP_STATE_lsb64(l_) + 1) +#define FM10K_SW_INGRESS_MST_TABLE_STP_STATE_DISABLE 0 +#define FM10K_SW_INGRESS_MST_TABLE_STP_STATE_LISTENING 1 +#define FM10K_SW_INGRESS_MST_TABLE_STP_STATE_LEARNING 2 +#define FM10K_SW_INGRESS_MST_TABLE_STP_STATE_FORWARD 3 +#define FM10K_SW_EGRESS_MST_TABLE(t_) \ + FM10K_SW_L2LOOKUP_REG(0x28800 + 0x2 * (t_)) +#define FM10K_SW_EGRESS_MST_TABLE_FORWARDING(l_) (1ULL << (l_)) +#define FM10K_SW_MA_TABLE_CFG_1 FM10K_SW_L2LOOKUP_REG(0x28A00) +#define FM10K_SW_MA_TABLE_CFG_2 FM10K_SW_L2LOOKUP_REG(0x28A02) +#define FM10K_SW_MTU_TABLE(n_) FM10K_SW_L2LOOKUP_REG(0x28A08 + (n_)) +#define FM10K_SW_IEEE_RESERVED_MAC_ACTION FM10K_SW_L2LOOKUP_REG(0x28A10) +#define FM10K_SW_IEEE_RESERVED_MAC_TRAP_PRIORITY FM10K_SW_L2LOOKUP_REG(0x28A14) +#define FM10K_SW_IEEE_RESERVED_MAC_CFG FM10K_SW_L2LOOKUP_REG(0x28A16) + + +#define FM10K_SW_GLORT_BASE FM10K_SW_REG_OFF(0xCE0000) +#define FM10K_SW_GLORT_REG(wo_) \ + (FM10K_SW_GLORT_BASE + FM10K_SW_REG_OFF(wo_)) +#define FM10K_SW_GLORT_CAM_ENTRIES 256 +#define FM10K_SW_GLORT_DEST_TABLE(n_) FM10K_SW_GLORT_REG(0x0 + 0x2 * (n_)) +#define FM10K_SW_GLORT_DEST_TABLE_MASK_lsb64 0 +#define FM10K_SW_GLORT_DEST_TABLE_MASK_msb64 47 +#define FM10K_SW_GLORT_DEST_TABLE_IP_MCAST_IDX_lsb64 48 +#define FM10K_SW_GLORT_DEST_TABLE_IP_MCAST_IDX_msb64 59 +#define FM10K_SW_GLORT_CAM(n_) FM10K_SW_GLORT_REG(0x2000 + (n_)) +#define FM10K_SW_GLORT_CAM_MATCH_ANY 0x00000000 +#define FM10K_SW_GLORT_CAM_MATCH_NONE FM10K_SW_MASK32(31, 0) +#define FM10K_SW_GLORT_CAM_KEY_lsb 0 +#define FM10K_SW_GLORT_CAM_KEY_msb 15 +#define FM10K_SW_GLORT_CAM_KEY_INVERT_lsb 16 +#define FM10K_SW_GLORT_CAM_KEY_INVERT_msb 31 +#define FM10K_SW_GLORT_RAM(n_) FM10K_SW_GLORT_REG(0x2200 + 0x2 * (n_)) +#define FM10K_SW_GLORT_RAM_STRICT_lsb64 0 +#define FM10K_SW_GLORT_RAM_STRICT_msb64 1 +#define FM10K_SW_GLORT_RAM_STRICT_FTYPE 0 +#define FM10K_SW_GLORT_RAM_STRICT_RSVD 1 +#define FM10K_SW_GLORT_RAM_STRICT_HASHED 2 +#define FM10K_SW_GLORT_RAM_STRICT_STRICT 3 +#define FM10K_SW_GLORT_RAM_DEST_INDEX_lsb64 2 +#define FM10K_SW_GLORT_RAM_DEST_INDEX_msb64 13 +#define FM10K_SW_GLORT_RAM_RANGE_SUBIDX_A_lsb64 14 +#define FM10K_SW_GLORT_RAM_RANGE_SUBIDX_A_msb64 21 +#define FM10K_SW_GLORT_RAM_RANGE_SUBIDX_B_lsb64 22 +#define FM10K_SW_GLORT_RAM_RANGE_SUBIDX_B_msb64 29 +#define FM10K_SW_GLORT_RAM_DEST_COUNT_lsb64 30 +#define FM10K_SW_GLORT_RAM_DEST_COUNT_msb64 33 +#define FM10K_SW_GLORT_RAM_HASH_ROTATION (1ULL << 34) + + +#define FM10K_SW_PARSER_BASE FM10K_SW_REG_OFF(0xCF0000) +#define FM10K_SW_PARSER_REG(wo_) \ + (FM10K_SW_PARSER_BASE + FM10K_SW_REG_OFF(wo_)) +#define FM10K_SW_PARSER_PORT_CFG_1(p_) \ + FM10K_SW_PARSER_REG(0x0 + 0x2 * (p_)) +#define FM10K_SW_PARSER_PORT_CFG_1_FTAG (1ULL << 0) +#define FM10K_SW_PARSER_PORT_CFG_1_VLAN1_TAG(v_) (1ULL << (1 + (v_))) +#define FM10K_SW_PARSER_PORT_CFG_1_VLAN2_TAG(v_) (1ULL << (5 + (v_))) +#define FM10K_SW_PARSER_PORT_CFG_1_VLAN2_FIRST (1ULL << 9) +#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VID_lsb 10 +#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VID_msb 21 +#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VPRI_lsb 22 +#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VPRI_msb 25 +#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VID2_lsb 26 +#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VID2_msb 37 +#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VPRI2_lsb 38 +#define FM10K_SW_PARSER_PORT_CFG_1_DEFAULT_VPRI2_msb 41 +#define FM10K_SW_PARSER_PORT_CFG_1_USE_DEFAULT_VLAN (1ULL << 42) +#define FM10K_SW_PARSER_PORT_CFG_2(p_) \ + FM10K_SW_PARSER_REG(0x80 + 0x2 * (p_)) +#define FM10K_SW_PARSER_PORT_CFG_2_CUSTOM_TAG_1_lsb 0 +#define FM10K_SW_PARSER_PORT_CFG_2_CUSTOM_TAG_1_msb 3 +#define FM10K_SW_PARSER_PORT_CFG_2_CUSTOM_TAG_2_lsb 4 +#define FM10K_SW_PARSER_PORT_CFG_2_CUSTOM_TAG_2_msb 7 +#define FM10K_SW_PARSER_PORT_CFG_2_PARSE_MPLS (1ULL << 8) +#define FM10K_SW_PARSER_PORT_CFG_2_STORE_MPLS_lsb 9 +#define FM10K_SW_PARSER_PORT_CFG_2_STORE_MPLS_msb 11 +#define FM10K_SW_PARSER_PORT_CFG_2_PARSE_L3 (1ULL << 12) +#define FM10K_SW_PARSER_PORT_CFG_2_PARSE_L4 (1ULL << 13) +#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV4_OPTIONS (1ULL << 14) +#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_HOP_BY_HOP (1ULL << 15) +#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_ROUTING (1ULL << 16) +#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_FRAG (1ULL << 17) +#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_DEST (1ULL << 18) +#define FM10K_SW_PARSER_PORT_CFG_2_FLAG_IPV6_AUTH (1ULL << 19) +#define FM10K_SW_PARSER_PORT_CFG_2_DEFAULT_DSCP_lsb 20 +#define FM10K_SW_PARSER_PORT_CFG_2_DEFAULT_DSCP_msb 25 +#define FM10K_SW_PARSER_PORT_CFG_2_DROP_TAGGED (1ULL << 26) +#define FM10K_SW_PARSER_PORT_CFG_2_DROP_UNTAGGED (1ULL << 27) +#define FM10K_SW_PARSER_PORT_CFG_2_USE_DEFAULT_DSCP (1ULL << 28) +#define FM10K_SW_PARSER_PORT_CFG_2_SWITCH_PRI_FROM_VLAN (1ULL << 29) +#define FM10K_SW_PARSER_PORT_CFG_2_SWITCH_PRI_FROM_DSCP (1ULL << 30) +#define FM10K_SW_PARSER_PORT_CFG_2_SWITCH_PRI_FROM_ISL (1ULL << 31) +#define FM10K_SW_PARSER_PORT_CFG_2_SWITCH_PRI_PREFER_DSCP (1ULL << 32) +#define FM10K_SW_PARSER_PORT_CFG_3(p_) FM10K_SW_PARSER_REG(0x100 + 0x2 * (p_)) +#define FM10K_SW_PORT_CFG_ISL(p_) FM10K_SW_PARSER_REG(0x180 + (p_)) +#define FM10K_SW_PORT_CFG_ISL_SGLORT_lsb 0 +#define FM10K_SW_PORT_CFG_ISL_SGLORT_msb 15 +#define FM10K_SW_PORT_CFG_ISL_USR_lsb 16 +#define FM10K_SW_PORT_CFG_ISL_USR_msb 23 +#define FM10K_SW_PORT_CFG_ISL_DEFAULT_PRI_lsb 24 +#define FM10K_SW_PORT_CFG_ISL_DEFAULT_PRI_msb 27 +#define FM10K_SW_PARSER_VLAN_TAG(n_) FM10K_SW_PARSER_REG(0x1C0 + (n_)) +#define FM10K_SW_PARSER_CUSTOM_TAG(n_) FM10K_SW_PARSER_REG(0x1C4 + (n_)) +#define FM10K_SW_PARSER_MPLS_TAG FM10K_SW_PARSER_REG(0x1C8) +#define FM10K_SW_PARSER_DI_CFG(n_) FM10K_SW_PARSER_REG(0x1D0 + 0x2 * (n_)) +#define FM10K_SW_RX_VPRI_MAP(p_) FM10K_SW_PARSER_REG(0x200 + 0x2 * (p_)) +#define FM10K_SW_DSCP_PRI_MAP(pri_) FM10K_SW_PARSER_REG(0x280 + (pri_)) +#define FM10K_SW_VPRI_PRI_MAP(pri_) FM10K_SW_PARSER_REG(0x2C0 + (pri_)) + + +#define FM10K_SW_HANDLER_BASE FM10K_SW_REG_OFF(0xD50000) +#define FM10K_SW_HANDLER_REG(wo_) \ + (FM10K_SW_HANDLER_BASE + FM10K_SW_REG_OFF(wo_)) + +#define FM10K_SW_SYS_CFG_1 FM10K_SW_HANDLER_REG(0x0) +#define FM10K_SW_SYS_CFG_1_DROP_PAUSE (1 << 0) +#define FM10K_SW_SYS_CFG_1_TRAP_MTU_VIOLATIONS (1 << 1) +#define FM10K_SW_SYS_CFG_1_ENABLE_TRAP_PLUS_LOG (1 << 2) +#define FM10K_SW_SYS_CFG_1_DROP_INVALID_SMAC (1 << 3) +#define FM10K_SW_SYS_CFG_1_DROP_MAC_CTRL_ETHERTYPE (1 << 4) +#define FM10K_SW_CPU_MAC FM10K_SW_HANDLER_REG(0x2) +#define FM10K_SW_SYS_CFG_ROUTER FM10K_SW_HANDLER_REG(0x4) +#define FM10K_SW_L34_HASH_CFG FM10K_SW_HANDLER_REG(0x5) +#define FM10K_SW_L34_HASH_CFG_SYMMETRIC (1 << 0) +#define FM10K_SW_L34_HASH_CFG_USE_SIP (1 << 1) +#define FM10K_SW_L34_HASH_CFG_USE_DIP (1 << 2) +#define FM10K_SW_L34_HASH_CFG_USE_PROT (1 << 3) +#define FM10K_SW_L34_HASH_CFG_USE_TCP (1 << 4) +#define FM10K_SW_L34_HASH_CFG_USE_UDP (1 << 5) +#define FM10K_SW_L34_HASH_CFG_USE_PROT1 (1 << 6) +#define FM10K_SW_L34_HASH_CFG_USE_PROT2 (1 << 7) +#define FM10K_SW_L34_HASH_CFG_USE_L4SRC (1 << 8) +#define FM10K_SW_L34_HASH_CFG_USE_L4DST (1 << 9) +#define FM10K_SW_L34_HASH_CFG_ECMP_ROTATION_lsb 10 +#define FM10K_SW_L34_HASH_CFG_ECMP_ROTATION_msb 11 +#define FM10K_SW_L34_HASH_CFG_PROT1_lsb 16 +#define FM10K_SW_L34_HASH_CFG_PROT1_msb 23 +#define FM10K_SW_L34_HASH_CFG_PROT2_lsb 24 +#define FM10K_SW_L34_HASH_CFG_PROT2_msb 31 +#define FM10K_SW_L34_FLOW_HASH_CFG_1 FM10K_SW_HANDLER_REG(0x6) +#define FM10K_SW_L34_FLOW_HASH_CFG_2 FM10K_SW_HANDLER_REG(0x7) +#define FM10K_SW_L234_HASH_CFG FM10K_SW_HANDLER_REG(0x8) +#define FM10K_SW_L234_HASH_CFG_USE_L2_IF_IP (1 << 0) +#define FM10K_SW_L234_HASH_CFG_USE_L34 (1 << 1) +#define FM10K_SW_L234_HASH_CFG_SYMMETRIC (1 << 2) +#define FM10K_SW_L234_HASH_CFG_USE_DMAC (1 << 3) +#define FM10K_SW_L234_HASH_CFG_USE_SMAC (1 << 4) +#define FM10K_SW_L234_HASH_CFG_USE_TYPE (1 << 5) +#define FM10K_SW_L234_HASH_CFG_USE_VPRI (1 << 6) +#define FM10K_SW_L234_HASH_CFG_USE_VID (1 << 8) +#define FM10K_SW_L234_HASH_CFG_ROTATION_A_lsb 8 +#define FM10K_SW_L234_HASH_CFG_ROTATION_A_msb 9 +#define FM10K_SW_L234_HASH_CFG_ROTATION_B_lsb 10 +#define FM10K_SW_L234_HASH_CFG_ROTATION_B_msb 11 +#define FM10K_SW_CPU_TRAP_MASK_FH FM10K_SW_HANDLER_REG(0xA) +#define FM10K_SW_TRAP_GLORT FM10K_SW_HANDLER_REG(0xC) +#define FM10K_SW_RX_MIRROR_CFG FM10K_SW_HANDLER_REG(0xD) +#define FM10K_SW_LOG_MIRROR_PROFILE FM10K_SW_HANDLER_REG(0xE) +#define FM10K_SW_FH_MIRROR_PROFILE_TABLE(n_) FM10K_SW_HANDLER_REG(0x40 + (n_)) +#define FM10K_SW_PORT_CFG_2(p_) FM10K_SW_HANDLER_REG(0x80 + 0x2 * (p_)) +#define FM10K_SW_PORT_CFG_3(p_) FM10K_SW_HANDLER_REG(0x100 + (p_)) +#define FM10K_SW_FH_LOOPBACK_SUPPRESS(p_) FM10K_SW_HANDLER_REG(0x140 + (p_)) +#define FM10K_SW_FH_HEAD_IP FM10K_SW_HANDLER_REG(0x180) +#define FM10K_SW_FH_HEAD_IM FM10K_SW_HANDLER_REG(0x182) +#define FM10K_SW_PARSER_EARLY_SRAM_CTRL FM10K_SW_HANDLER_REG(0x184) +#define FM10K_SW_PARSER_LATE_SRAM_CTRL FM10K_SW_HANDLER_REG(0x185) +#define FM10K_SW_MAPPER_SRAM_CTRL FM10K_SW_HANDLER_REG(0x186) +#define FM10K_SW_FFU_SRAM_CTRL(n_) FM10K_SW_HANDLER_REG(0x1A0 + 0x4 * (n_)) +#define FM10K_SW_ARP_SRAM_CTRL FM10K_SW_HANDLER_REG(0x1C0) +#define FM10K_SW_VLAN_LOOKUP_SRAM_CTRL FM10K_SW_HANDLER_REG(0x1C1) +#define FM10K_SW_MA_TABLE_SRAM_CTRL(n_) FM10K_SW_HANDLER_REG(0x1C4 + 0x2 * (n_)) +#define FM10K_SW_FID_GLORT_LOOKUP_SRAM_CTRL FM10K_SW_HANDLER_REG(0x1C8) +#define FM10K_SW_GLORT_RAM_SRAM_CTRL FM10K_SW_HANDLER_REG(0x1CA) +#define FM10K_SW_GLORT_TABLE_SRAM_CTRL FM10K_SW_HANDLER_REG(0x1CB) +#define FM10K_SW_FH_HEAD_OUTPUT_FIFO_SRAM_CTRL FM10K_SW_HANDLER_REG(0x1CC) + + +#define FM10K_SW_LAG_BASE FM10K_SW_REG_OFF(0xD90000) +#define FM10K_SW_LAG_REG(wo_) (FM10K_SW_LAG_BASE + FM10K_SW_REG_OFF(wo_)) +#define FM10K_SW_LAG_CFG(l_) FM10K_SW_LAG_REG(l_) +#define FM10K_SW_LAG_CFG_LAG_SIZE_lsb 0 +#define FM10K_SW_LAG_CFG_LAG_SIZE_msb 3 +#define FM10K_SW_LAG_CFG_INDEX_lsb 4 +#define FM10K_SW_LAG_CFG_INDEX_msb 7 +#define FM10K_SW_LAG_CFG_HASH_ROTATION (1 << 8) +#define FM10K_SW_LAG_CFG_IN_LAG (1 << 9) +#define FM10K_SW_CANONICAL_GLORT_CAM(n_) FM10K_SW_LAG_REG((n_) + 0x40) +#define FM10K_SW_CANONICAL_GLORT_CAM_LAG_GLORT_lsb 0 +#define FM10K_SW_CANONICAL_GLORT_CAM_LAG_GLORT_msb 15 +#define FM10K_SW_CANONICAL_GLORT_CAM_MASK_SIZE_lsb 16 +#define FM10K_SW_CANONICAL_GLORT_CAM_MASK_SIZE_msb 19 +#define FM10K_SW_CANONICAL_GLORT_CAM_PORT_FIELD_SIZE_lsb 20 +#define FM10K_SW_CANONICAL_GLORT_CAM_PORT_FIELD_SIZE_msb 22 + + +#define FM10K_SW_RX_STATS_BASE FM10K_SW_REG_OFF(0xE00000) +#define FM10K_SW_RX_STATS_REG(wo_) \ + (FM10K_SW_RX_STATS_BASE + FM10K_SW_REG_OFF(wo_)) +#define FM10K_SW_RX_STATS_BANK(b_, i_) \ + FM10K_SW_RX_STATS_REG(0x1000 * (b_) + 0x4 * (i_)) +#define FM10K_SW_RX_STATS_BANK_1_INDEX 0 +#define FM10K_SW_RX_STATS_BANK_2_INDEX 1 +#define FM10K_SW_RX_STATS_BANK_3_INDEX 2 +#define FM10K_SW_RX_STATS_BANK_4_INDEX 3 +#define FM10K_SW_RX_STATS_BANK_5_INDEX 4 +#define FM10K_SW_RX_STATS_BANK_6_INDEX 5 +#define FM10K_SW_RX_STATS_BANK_1_NON_IP_L2_UCAST 0 +#define FM10K_SW_RX_STATS_BANK_1_NON_IP_L2_MCAST 1 +#define FM10K_SW_RX_STATS_BANK_1_NON_IP_L2_BCAST 2 +#define FM10K_SW_RX_STATS_BANK_1_IPV4_L2_UCAST 3 +#define FM10K_SW_RX_STATS_BANK_1_IPV4_L2_MCAST 4 +#define FM10K_SW_RX_STATS_BANK_1_IPV4_L2_BCAST 5 +#define FM10K_SW_RX_STATS_BANK_1_IPV6_L2_UCAST 6 +#define FM10K_SW_RX_STATS_BANK_1_IPV6_L2_MCAST 7 +#define FM10K_SW_RX_STATS_BANK_1_IPV6_L2_BCAST 8 +#define FM10K_SW_RX_STATS_BANK_1_IEEE802_3_PAUSE 9 +#define FM10K_SW_RX_STATS_BANK_1_CLASS_BASED_PAUSE 10 +#define FM10K_SW_RX_STATS_BANK_1_FRAMING_ERR 11 +#define FM10K_SW_RX_STATS_BANK_1_FCS_ERR 12 +#define FM10K_SW_RX_STATS_BANK_2_LEN_LT_64 0 +#define FM10K_SW_RX_STATS_BANK_2_LEN_EQ_64 1 +#define FM10K_SW_RX_STATS_BANK_2_LEN_65_127 2 +#define FM10K_SW_RX_STATS_BANK_2_LEN_128_255 3 +#define FM10K_SW_RX_STATS_BANK_2_LEN_256_511 4 +#define FM10K_SW_RX_STATS_BANK_2_LEN_512_1023 5 +#define FM10K_SW_RX_STATS_BANK_2_LEN_1024_1522 6 +#define FM10K_SW_RX_STATS_BANK_2_LEN_1523_2047 7 +#define FM10K_SW_RX_STATS_BANK_2_LEN_2048_4095 8 +#define FM10K_SW_RX_STATS_BANK_2_LEN_4096_8191 9 +#define FM10K_SW_RX_STATS_BANK_2_LEN_8192_10239 10 +#define FM10K_SW_RX_STATS_BANK_2_LEN_GE_10240 11 +#define FM10K_SW_RX_STATS_BANK_3_PRI(p_) (p_) +#define FM10K_SW_RX_STATS_BANK_4_FID_FORWARDED 0 +#define FM10K_SW_RX_STATS_BANK_4_FLOOD_FORWARDED 1 +#define FM10K_SW_RX_STATS_BANK_4_SPECIALLY_HANDLED 2 +#define FM10K_SW_RX_STATS_BANK_4_PARSER_ERROR_DROP 3 +#define FM10K_SW_RX_STATS_BANK_4_ECC_ERROR_DROP 4 +#define FM10K_SW_RX_STATS_BANK_4_TRAPPED 5 +#define FM10K_SW_RX_STATS_BANK_4_PAUSE_DROPS 6 +#define FM10K_SW_RX_STATS_BANK_4_STP_DROPS 7 +#define FM10K_SW_RX_STATS_BANK_4_SECURITY_VIOLATIONS 8 +#define FM10K_SW_RX_STATS_BANK_4_VLAN_TAG_DROPS 9 +#define FM10K_SW_RX_STATS_BANK_4_VLAN_INGRESS_DROPS 10 +#define FM10K_SW_RX_STATS_BANK_4_VLAN_EGRESS_DROPS 11 +#define FM10K_SW_RX_STATS_BANK_4_GLORT_MISS_DROPS 12 +#define FM10K_SW_RX_STATS_BANK_4_FFU_DROPS 13 +#define FM10K_SW_RX_STATS_BANK_4_TRIGGER_DROPS 14 +#define FM10K_SW_RX_STATS_BANK_5_POLICER_DROPS 0 +#define FM10K_SW_RX_STATS_BANK_5_TTL_DROPS 1 +#define FM10K_SW_RX_STATS_BANK_5_CM_PRIV_DROPS 2 +#define FM10K_SW_RX_STATS_BANK_5_CM_SMP0_DROPS 3 +#define FM10K_SW_RX_STATS_BANK_5_CM_SMP1_DROPS 4 +#define FM10K_SW_RX_STATS_BANK_5_CM_RX_HOG0_DROPS 5 +#define FM10K_SW_RX_STATS_BANK_5_CM_RX_HOG1_DROPS 6 +#define FM10K_SW_RX_STATS_BANK_5_CM_TX_HOG0_DROPS 7 +#define FM10K_SW_RX_STATS_BANK_5_CM_TX_HOG1_DROPS 8 +#define FM10K_SW_RX_STATS_BANK_5_TRIGGER_REDIRECTS 10 +#define FM10K_SW_RX_STATS_BANK_5_FLOOD_CONTROL_DROPS 11 +#define FM10K_SW_RX_STATS_BANK_5_GLORT_FORWARDED 12 +#define FM10K_SW_RX_STATS_BANK_5_LOOPBACK_SUPP_DROPS 13 +#define FM10K_SW_RX_STATS_BANK_5_OTHER_DROPS 14 +#define FM10K_SW_RX_PORT_STAT(b_, s_, p_, f_) \ + (FM10K_SW_RX_STATS_BANK(FM10K_SW_RX_STATS_##b_##_INDEX, \ + 16 * (p_) + FM10K_SW_RX_STATS_##b_##_##s_) + \ + ((f_) ? 0 : FM10K_SW_REG_OFF(2))) +#define FM10K_SW_RX_STATS_CFG(p_) FM10K_SW_RX_STATS_REG(0x10000 + (p_)) +#define FM10K_SW_RX_STATS_CFG_PER_FRAME_ADJUSTMENT_lsb 0 +#define FM10K_SW_RX_STATS_CFG_PER_FRAME_ADJUSTMENT_msb 7 +#define FM10K_SW_RX_STATS_CFG_ENABLE_ALL_BANKS 0x00003f00 +#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_1 (1 << 8) +#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_2 (1 << 9) +#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_3 (1 << 10) +#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_4 (1 << 11) +#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_5 (1 << 12) +#define FM10K_SW_RX_STATS_CFG_ENABLE_BANK_6 (1 << 13) +#define FM10K_SW_RX_STATS_CFG_SWITCH_PRI (1 << 14) + + +#define FM10K_SW_HANDLER_TAIL_BASE FM10K_SW_REG_OFF(0xE30000) +#define FM10K_SW_HANDLER_TAIL_REG(wo_) \ + (FM10K_SW_HANDLER_TAIL_BASE + FM10K_SW_REG_OFF(wo_)) +#define FM10K_SW_SAF_MATRIX(l_) FM10K_SW_HANDLER_TAIL_REG(0x2 * (l_)) +#define FM10K_SW_SAF_MATRIX_ENABLE_SNF(l_) (1ULL << (l_)) +#define FM10K_SW_SAF_MATRIX_ENABLE_SNF_ALL_PORTS FM10K_SW_MASK64(47, 0) +#define FM10K_SW_SAF_MATRIX_IGNORE_ERROR (1ULL << 50) +#define FM10K_SW_FRAME_TIME_OUT FM10K_SW_HANDLER_TAIL_REG(0x80) +#define FM10K_SW_SAF_SRAM_CTRL FM10K_SW_HANDLER_TAIL_REG(0x81) +#define FM10K_SW_EGRESS_PAUSE_SRAM_CTRL FM10K_SW_HANDLER_TAIL_REG(0x82) +#define FM10K_SW_RX_STATS_SRAM_CTRL FM10K_SW_HANDLER_TAIL_REG(0x84) +#define FM10K_SW_POLICER_USAGE_SRAM_CTRL FM10K_SW_HANDLER_TAIL_REG(0x88) +#define FM10K_SW_TCN_SRAM_CTRL FM10K_SW_HANDLER_TAIL_REG(0x8C) +#define FM10K_SW_FH_TAIL_IP FM10K_SW_HANDLER_TAIL_REG(0x8D) +#define FM10K_SW_FH_TAIL_IM FM10K_SW_HANDLER_TAIL_REG(0x8E) +#define FM10K_SW_TAIL_PERMIT_MGMT FM10K_SW_HANDLER_TAIL_REG(0x8F) +#define FM10K_SW_TAIL_FORCE_IDLE FM10K_SW_HANDLER_TAIL_REG(0x90) + + +#define FM10K_SW_CM_USAGE_BASE FM10K_SW_REG_OFF(0xE60000) +#define FM10K_SW_CM_USAGE_REG(wo_) \ + (FM10K_SW_CM_USAGE_BASE + FM10K_SW_REG_OFF(wo_)) +#define FM10K_SW_CM_SWEEPER_SWITCH_PRI_TO_TC FM10K_SW_CM_USAGE_REG(0x0) +#define FM10K_SW_CM_SWEEPER_TC_TO_SMP FM10K_SW_CM_USAGE_REG(0x2) +#define FM10K_SW_CM_TX_TC_PRIVATE_WM(l_, c_) \ + FM10K_SW_CM_USAGE_REG(0x200 + 0x8 * (l_) + (c_)) +#define FM10K_SW_CM_TX_TC_HOG_WM(l_, c_) \ + FM10K_SW_CM_USAGE_REG(0x400 + 0x8 * (l_) + (c_)) +#define FM10K_SW_CM_RX_SMP_PAUSE_WM(l_, s_) \ + FM10K_SW_CM_USAGE_REG(0x600 + 0x2 * (l_) + (s_)) +#define FM10K_SW_CM_RX_SMP_PRIVATE_WM(l_, s_) \ + FM10K_SW_CM_USAGE_REG(0x680 + 0x2 * (l_) + (s_)) +#define FM10K_SW_CM_RX_SMP_HOG_WM(l_, s_) \ + FM10K_SW_CM_USAGE_REG(0x700 + 0x2 * (l_) + (s_)) +#define FM10K_SW_CM_PAUSE_RESEND_INTERVAL(l_) \ + FM10K_SW_CM_USAGE_REG(0x780 + (l_)) +#define FM10K_SW_CM_PAUSE_BASE_FREQ \ + FM10K_SW_CM_USAGE_REG(0x7C0) +#define FM10K_SW_CM_PAUSE_CFG(l_) \ + FM10K_SW_CM_USAGE_REG(0x800 + (l_)) +#define FM10K_SW_CM_SHARED_WM(p_) \ + FM10K_SW_CM_USAGE_REG(0x840 + (p_)) +#define FM10K_SW_CM_SHARED_SMP_PAUSE_WM(s_) \ + FM10K_SW_CM_USAGE_REG(0x850 + (s_)) +#define FM10K_SW_CM_GLOBAL_WM FM10K_SW_CM_USAGE_REG(0x852) +#define FM10K_SW_CM_GLOBAL_WM_WATERMARK_lsb 0 +#define FM10K_SW_CM_GLOBAL_WM_WATERMARK_msb 14 +#define FM10K_SW_CM_GLOBAL_CFG FM10K_SW_CM_USAGE_REG(0x853) +#define FM10K_SW_CM_GLOBAL_CFG_IFG_PENALTY_lsb 0 +#define FM10K_SW_CM_GLOBAL_CFG_IFG_PENALTY_msb 7 +#define FM10K_SW_CM_GLOBAL_CFG_FORCE_PAUSE_ON (1 << 8) +#define FM10K_SW_CM_GLOBAL_CFG_FORCE_PAUSE_OFF (1 << 9) +#define FM10K_SW_CM_GLOBAL_CFG_WM_SWEEP_EN (1 << 10) +#define FM10K_SW_CM_GLOBAL_CFG_PAUSE_GEN_SWEEP_EN (1 << 11) +#define FM10K_SW_CM_GLOBAL_CFG_PAUSE_REC_SWEEP_EN (1 << 12) +#define FM10K_SW_CM_GLOBAL_CFG_NUM_SWEEPER_PORTS_lsb 13 +#define FM10K_SW_CM_GLOBAL_CFG_NUM_SWEEPER_PORTS_msb 18 +#define FM10K_SW_CM_TC_PC_MAP(l_) FM10K_SW_CM_USAGE_REG(0x880 + (l_)) +#define FM10K_SW_CM_PC_SMP_MAP(l_) FM10K_SW_CM_USAGE_REG(0x8C0 + (l_)) +#define FM10K_SW_CM_SOFTDROP_WM(p_) FM10K_SW_CM_USAGE_REG(0x900 + (p_)) +#define FM10K_SW_CM_SHARED_SMP_PAUSE_CFG(s_) \ + FM10K_SW_CM_USAGE_REG(0x910 + 0x2 * (s_)) +#define FM10K_SW_TX_RATE_LIM_CFG(l_, c_) \ + FM10K_SW_CM_USAGE_REG(0xA00 + 0x8 * (l_) + (c_)) +#define FM10K_SW_TX_RATE_LIM_USAGE(l_, c_) \ + FM10K_SW_CM_USAGE_REG(0xC00 + 0x8 * (l_) + (c_)) +#define FM10K_SW_CM_BSG_MAP(l_) \ + FM10K_SW_CM_USAGE_REG(0xE00 + (l_)) +#define FM10K_SW_CM_TX_TC_USAGE(l_, c_) \ + FM10K_SW_CM_USAGE_REG(0x1000 + 0x8 * (l_) + (c_)) +#define FM10K_SW_CM_RX_SMP_USAGE(l_, s_) \ + FM10K_SW_CM_USAGE_REG(0x1200 + 0x2 * (l_) + (s_)) +#define FM10K_SW_MCAST_EPOCH_USAGE(s_) \ + FM10K_SW_CM_USAGE_REG(0x1280 + (s_)) +#define FM10K_SW_CM_SHARED_SMP_USAGE(s_) \ + FM10K_SW_CM_USAGE_REG(0x1282 + (s_)) +#define FM10K_SW_CM_SMP_USAGE(s_) \ + FM10K_SW_CM_USAGE_REG(0x1284 + (s_)) +#define FM10K_SW_CM_GLOBAL_USAGE FM10K_SW_CM_USAGE_REG(0x1286) +#define FM10K_SW_CM_PAUSE_GEN_STATE(l_) FM10K_SW_CM_USAGE_REG(0x12C0 + (l_)) +#define FM10K_SW_CM_PAUSE_RCV_TIMER FM10K_SW_CM_USAGE_REG(0x1300) +#define FM10K_SW_CM_PAUSE_RCV_PORT_TIMER(l_) \ + FM10K_SW_CM_USAGE_REG(0x1340 + (l_)) + +/* FM10K_SW_CM_EGRESS_PAUSE_COUNT is also + * known as FM10K_SW_CM_PAUSE_RCV_STATE + */ +#define FM10K_SW_CM_EGRESS_PAUSE_COUNT(l_, dw_) \ + FM10K_SW_CM_USAGE_REG(0x1400 + 0x4 * (l_) + 0x2 * (dw_)) + +#define FM10K_SW_MOD_BASE FM10K_SW_REG_OFF(0xE80000) +#define FM10K_SW_MOD_REG(wo_) \ + (FM10K_SW_MOD_BASE + FM10K_SW_REG_OFF(wo_)) + +#define FM10K_SW_MOD_MAX_MGMT_WAIT_CYCLE FM10K_SW_MOD_REG(0xF8) +#define FM10K_SW_MOD_IP FM10K_SW_MOD_REG(0x106) +#define FM10K_SW_MOD_IM FM10K_SW_MOD_REG(0x108) +#define FM10K_SW_MOD_SRAM_BIST_OUT FM10K_SW_MOD_REG(0x10A) +#define FM10K_SW_MOD_SRAM_ERROR_WRITE FM10K_SW_MOD_REG(0x10C) +#define FM10K_SW_MOD_PAUSE_SMAC FM10K_SW_MOD_REG(0x10E) +#define FM10K_SW_MOD_ROUTER_SMAC(n_) FM10K_SW_MOD_REG(0x120 + 0x2 * (n_)) +#define FM10K_SW_MOD_MCAST_VLAN_TABLE(n_) \ + FM10K_SW_MOD_REG(0x10000 + 0x2 * (n_)) +#define FM10K_SW_MOD_VLAN_TAG_VID1_MAP(v_) \ + FM10K_SW_MOD_REG(0x20000 + 0x2 * (v_)) +#define FM10K_SW_MOD_VID2_MAP(v_) \ + FM10K_SW_MOD_REG(0x22000 + 0x2 * (v_)) +#define FM10K_SW_MOD_MIRROR_PROFILE_TABLE(n_) \ + FM10K_SW_MOD_REG(0x24000 + 0x2 * (n_)) +#define FM10K_SW_MOD_PER_PORT_CFG_1(p_) \ + FM10K_SW_MOD_REG(0x24080 + 0x2 * (p_)) +#define FM10K_SW_MOD_PER_PORT_CFG_2(p_) \ + FM10K_SW_MOD_REG(0x24100 + 0x2 * (p_)) +#define FM10K_SW_MOD_PER_PORT_CFG_2_MIRROR_TRUNCATION_LEN_lsb64 0 +#define FM10K_SW_MOD_PER_PORT_CFG_2_MIRROR_TRUNCATION_LEN_msb64 5 +#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_PCP1_UPDATE (1ULL << 6) +#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_PCP2_UPDATE (1ULL << 7) +#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_DEI1_UPDATE (1ULL << 8) +#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_DEI2_UPDATE (1ULL << 9) +#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN1_ETYPE_lsb64 10 +#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN1_ETYPE_msb64 11 +#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN2_ETYPE_lsb64 12 +#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN2_ETYPE_msb64 13 +#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_DMAC_ROUTING (1ULL << 14) +#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_SMAC_ROUTING (1ULL << 15) +#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_TTL_DECREMENT (1ULL << 16) +#define FM10K_SW_MOD_PER_PORT_CFG_2_ENABLE_DSCP_MODIFICATION (1ULL << 17) +#define FM10K_SW_MOD_PER_PORT_CFG_2_FTAG (1ULL << 18) +#define FM10K_SW_MOD_PER_PORT_CFG_2_VID2_FIRST (1ULL << 19) +#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN_TAGGING_lsb64 20 +#define FM10K_SW_MOD_PER_PORT_CFG_2_VLAN_TAGGING_msb64 22 +#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_PRI_EN_VEC_lsb64 23 +#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_PRI_EN_VEC_msb64 30 +#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_TYPE (1ULL << 31) +#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_VALUE_lsb64 32 +#define FM10K_SW_MOD_PER_PORT_CFG_2_TX_PAUSE_VALUE_msb64 47 +#define FM10K_SW_MOD_PER_PORT_CFG_2_MIN_FRAME_SIZE (1ULL << 48) +#define FM10K_SW_MOD_VPRI1_MAP(p_) \ + FM10K_SW_MOD_REG(0x24180 + 0x2 * (p_)) +#define FM10K_SW_MOD_VPRI2_MAP(p_) \ + FM10K_SW_MOD_REG(0x24200 + 0x2 * (p_)) +#define FM10K_SW_MOD_VLAN_ETYPE(n_) \ + FM10K_SW_MOD_REG(0x24280 + 0x2 * (n_)) +#define FM10K_SW_MOD_STATS_CFG(p_) \ + FM10K_SW_MOD_REG(0x24300 + 0x2 * (p_)) +#define FM10K_SW_MOD_STATS_CFG_ENABLE_GROUP_7 (1 << 0) +#define FM10K_SW_MOD_STATS_CFG_ENABLE_GROUP_8 (1 << 1) +#define FM10K_SW_MOD_STATS_BANK_FRAME(b_, i_) \ + FM10K_SW_MOD_REG(0x25000 + 0x800 * (b_) + 0x2 * (i_)) +#define FM10K_SW_MOD_STATS_BANK_BYTE(b_, i_) \ + FM10K_SW_MOD_REG(0x26000 + 0x800 * (b_) + 0x2 * (i_)) +#define FM10K_SW_MOD_STATS_BANK_7_INDEX 0 +#define FM10K_SW_MOD_STATS_BANK_8_INDEX 1 +#define FM10K_SW_MOD_STATS_BANK_7_L2_UCAST 0 +#define FM10K_SW_MOD_STATS_BANK_7_L2_MCAST 1 +#define FM10K_SW_MOD_STATS_BANK_7_L2_BCAST 2 +#define FM10K_SW_MOD_STATS_BANK_7_TX_ERROR 3 +#define FM10K_SW_MOD_STATS_BANK_7_TIMEOUT_DROP 4 +#define FM10K_SW_MOD_STATS_BANK_7_TX_ERROR_DROP 5 +#define FM10K_SW_MOD_STATS_BANK_7_TX_ECC_DROP 6 +#define FM10K_SW_MOD_STATS_BANK_7_LOOPBACK_DROP 7 +#define FM10K_SW_MOD_STATS_BANK_7_TTL1_DROP 8 +#define FM10K_SW_MOD_STATS_BANK_7_PAUSE 9 +#define FM10K_SW_MOD_STATS_BANK_7_CB_PAUSE 10 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_LT_64 0 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_EQ_64 1 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_65_127 2 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_128_255 3 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_256_511 4 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_512_1023 5 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_1024_1522 6 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_1523_2047 7 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_2048_4095 8 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_4096_8191 9 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_8192_10239 10 +#define FM10K_SW_MOD_STATS_BANK_8_LEN_GE_10240 11 +#define FM10K_SW_TX_PORT_STAT(b_, s_, p_, f_, p1_) \ + ((f_) ? \ + FM10K_SW_MOD_STATS_BANK_FRAME(FM10K_SW_MOD_STATS_##b_##_INDEX, \ + 16 * (p_) + FM10K_SW_MOD_STATS_##b_##_##s_) : \ + FM10K_SW_MOD_STATS_BANK_BYTE(FM10K_SW_MOD_STATS_##b_##_INDEX, \ + 16 * (p1_) + FM10K_SW_MOD_STATS_##b_##_##s_)) + +#define FM10K_SW_SCHED_BASE FM10K_SW_REG_OFF(0xF00000) +#define FM10K_SW_SCHED_REG(wo_) \ + (FM10K_SW_SCHED_BASE + FM10K_SW_REG_OFF(wo_)) + +/* + * Schedule fields for both FM10K_SW_SCHED_RX_SCHEDULE and + * FM10K_SW_SCHED_TX_SCHEDULE + */ +#define FM10K_SW_SCHED_SCHEDULE_ENTRY(p_, l_, q_) \ + (FM10K_SW_MAKE_REG_FIELD(SCHED_SCHEDULE_PHYS_PORT, (p_)) | \ + FM10K_SW_MAKE_REG_FIELD(SCHED_SCHEDULE_LOG_PORT, (l_)) | \ + ((q_) ? FM10K_SW_SCHED_SCHEDULE_QUAD : 0)) +#define FM10K_SW_SCHED_SCHEDULE_PHYS_PORT_lsb 0 +#define FM10K_SW_SCHED_SCHEDULE_PHYS_PORT_msb 7 +#define FM10K_SW_SCHED_SCHEDULE_LOG_PORT_lsb 8 +#define FM10K_SW_SCHED_SCHEDULE_LOG_PORT_msb 13 +#define FM10K_SW_SCHED_SCHEDULE_QUAD (1 << 14) +#define FM10K_SW_SCHED_SCHEDULE_COLOR (1 << 15) +#define FM10K_SW_SCHED_SCHEDULE_IDLE (1 << 16) + +#define FM10K_SW_SCHED_RX_SCHEDULE(p_, n_) \ + FM10K_SW_SCHED_REG(0x20000 + 0x200 * (p_) + (n_)) +#define FM10K_SW_SCHED_TX_SCHEDULE(p_, n_) \ + FM10K_SW_SCHED_REG(0x20400 + 0x200 * (p_) + (n_)) +#define FM10K_SW_SCHED_SCHEDULE_CTRL FM10K_SW_SCHED_REG(0x20800) +#define FM10K_SW_SCHED_SCHEDULE_CTRL_RX_ENABLE (1 << 0) +#define FM10K_SW_SCHED_SCHEDULE_CTRL_RX_PAGE (1 << 1) +#define FM10K_SW_SCHED_SCHEDULE_CTRL_RX_MAX_INDEX_lsb 2 +#define FM10K_SW_SCHED_SCHEDULE_CTRL_RX_MAX_INDEX_msb 10 +#define FM10K_SW_SCHED_SCHEDULE_CTRL_TX_ENABLE (1 << 11) +#define FM10K_SW_SCHED_SCHEDULE_CTRL_TX_PAGE (1 << 12) +#define FM10K_SW_SCHED_SCHEDULE_CTRL_TX_MAX_INDEX_lsb 13 +#define FM10K_SW_SCHED_SCHEDULE_CTRL_TX_MAX_INDEX_msb 21 +#define FM10K_SW_SCHED_CONFIG_SRAM_CTRL \ + FM10K_SW_SCHED_REG(0x20801) +#define FM10K_SW_SCHED_SSCHED_RX_PERPORT(l_) \ + FM10K_SW_SCHED_REG(0x20840 + (l_)) +#define FM10K_SW_SCHED_SSCHED_RX_PERPORT_NEXT_lsb 0 +#define FM10K_SW_SCHED_SSCHED_RX_PERPORT_NEXT_msb 15 +#define FM10K_SW_SCHED_SSCHED_SRAM_CTRL FM10K_SW_SCHED_REG(0x30050) +#define FM10K_SW_SCHED_ESCHED_CFG_1(l_) FM10K_SW_SCHED_REG(0x30080 + (l_)) +#define FM10K_SW_SCHED_ESCHED_CFG_2(l_) FM10K_SW_SCHED_REG(0x300C0 + (l_)) +#define FM10K_SW_SCHED_ESCHED_CFG_3(l_) FM10K_SW_SCHED_REG(0x30100 + (l_)) +#define FM10K_SW_SCHED_MGMT_TIMER_ESCHED FM10K_SW_SCHED_REG(0x30240) +#define FM10K_SW_SCHED_ESCHED_SRAM_CTRL FM10K_SW_SCHED_REG(0x30242) +#define FM10K_SW_SCHED_FREELIST_INIT FM10K_SW_SCHED_REG(0x30244) +#define FM10K_SW_SCHED_FREELIST_INIT_ENTRIES (24 * 1024) +#define FM10K_SW_SCHED_FREELIST_INIT_ADDRESS_lsb 0 +#define FM10K_SW_SCHED_FREELIST_INIT_ADDRESS_msb 15 +#define FM10K_SW_SCHED_FREELIST_SRAM_CTRL FM10K_SW_SCHED_REG(0x30246) +#define FM10K_SW_SCHED_MONITOR_DRR_Q_PERQ(q_) \ + FM10K_SW_SCHED_REG(0x30400 + (q_)) +#define FM10K_SW_SCHED_MONITOR_DRR_CFG_PERPORT(l_) \ + FM10K_SW_SCHED_REG(0x30600 + (l_)) +#define FM10K_SW_SCHED_MGMT_TIMER_MONITOR FM10K_SW_SCHED_REG(0x30A40) +#define FM10K_SW_SCHED_MONITOR_SRAM_CTRL FM10K_SW_SCHED_REG(0x30A41) +#define FM10K_SW_SCHED_MCAST_LEN_TABLE(n_) \ + FM10K_SW_SCHED_REG(0x34000 + (n_)) +#define FM10K_SW_SCHED_MCAST_DEST_TABLE(n_) \ + FM10K_SW_SCHED_REG(0x38000 + 0x2 * (n_)) +#define FM10K_SW_SCHED_MCAST_LIMITED_SKEW_MULTICAST \ + FM10K_SW_SCHED_REG(0x3A000) +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS(n_) \ + FM10K_SW_SCHED_REG(0x60400 + 0x2 * (n_)) +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_ENTRIES 8 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_HEAD_PAGE_lsb 0 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_HEAD_PAGE_msb 9 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_TAIL_PAGE_lsb 10 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_TAIL_PAGE_msb 19 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_HEAD_IDX_lsb 20 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_HEAD_IDX_msb 24 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_TAIL_IDX_lsb 25 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_TAIL_IDX_msb 29 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_NEXT_PAGE_lsb 30 +#define FM10K_SW_SCHED_RXQ_STORAGE_POINTERS_NEXT_PAGE_msb 39 +#define FM10K_SW_SCHED_RXQ_FREELIST_INIT FM10K_SW_SCHED_REG(0x60410) +#define FM10K_SW_SCHED_RXQ_FREELIST_INIT_ENTRIES 1024 +#define FM10K_SW_SCHED_RXQ_FREELIST_INIT_ADDRESS_lsb 0 +#define FM10K_SW_SCHED_RXQ_FREELIST_INIT_ADDRESS_msb 9 +#define FM10K_SW_SCHED_MGMT_TIMER_RXQ FM10K_SW_SCHED_REG(0x60412) +#define FM10K_SW_SCHED_MGMT_TIMER_LG FM10K_SW_SCHED_REG(0x60413) +#define FM10K_SW_SCHED_RXQ_SRAM_CTRL FM10K_SW_SCHED_REG(0x60414) +#define FM10K_SW_SCHED_TXQ_TAIL0_PERQ(q_) \ + FM10K_SW_SCHED_REG(0x60600 + (q_)) +#define FM10K_SW_SCHED_TXQ_TAIL0_PERQ_TAIL_lsb 0 +#define FM10K_SW_SCHED_TXQ_TAIL0_PERQ_TAIL_msb 15 +#define FM10K_SW_SCHED_TXQ_TAIL1_PERQ(q_) \ + FM10K_SW_SCHED_REG(0x60800 + (q_)) +#define FM10K_SW_SCHED_TXQ_TAIL1_PERQ_TAIL_lsb 0 +#define FM10K_SW_SCHED_TXQ_TAIL1_PERQ_TAIL_msb 15 +#define FM10K_SW_SCHED_TXQ_HEAD_PERQ(q_) \ + FM10K_SW_SCHED_REG(0x60A00 + (q_)) +#define FM10K_SW_SCHED_TXQ_HEAD_PERQ_ENTRIES 384 +#define FM10K_SW_SCHED_TXQ_HEAD_PERQ_HEAD_lsb 0 +#define FM10K_SW_SCHED_TXQ_HEAD_PERQ_HEAD_msb 15 +#define FM10K_SW_SCHED_TXQ_FREELIST_INIT FM10K_SW_SCHED_REG(0x62000) +#define FM10K_SW_SCHED_TXQ_FREELIST_INIT_ENTRIES (24 * 1024) +#define FM10K_SW_SCHED_TXQ_FREELIST_INIT_ADDRESS_lsb 0 +#define FM10K_SW_SCHED_TXQ_FREELIST_INIT_ADDRESS_msb 15 +#define FM10K_SW_SCHED_TXQ_SRAM_CTRL FM10K_SW_SCHED_REG(0x62002) +#define FM10K_SW_SCHED_FIFO_SRAM_CTRL FM10K_SW_SCHED_REG(0x62004) +#define FM10K_SW_SCHED_IP FM10K_SW_SCHED_REG(0x62006) +#define FM10K_SW_SCHED_IM FM10K_SW_SCHED_REG(0x62007) + +#endif /* _FM10K_REGS_H_ */ diff --git a/drivers/net/fm10k/switch/fm10k_sbus.c b/drivers/net/fm10k/switch/fm10k_sbus.c new file mode 100644 index 0000000..d7d656e --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_sbus.c @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include "fm10k_debug.h" +#include "fm10k_regs.h" +#include "fm10k_sbus.h" +#include "fm10k_switch.h" + +#define FM10K_SW_SBUS_COMMAND_WAIT_LOCK_US_MAX 4 +#define FM10K_SW_SBUS_COMMAND_TIMEOUT_US 500000 +#define FM10K_SW_SBUS_RING_DIVIDER 0x01 + +static int fm10k_sbus_init(struct fm10k_sbus *); +static int fm10k_sbus_exec(struct fm10k_sbus *, struct fm10k_sbus_req *); +static int fm10k_sbus_reset_all(struct fm10k_sbus *); +static int fm10k_sbus_sbm_reset(struct fm10k_sbus *); + +struct fm10k_sbus * +fm10k_sbus_attach(struct fm10k_switch *sw, + const char *name, + unsigned int cfg_reg) +{ + struct fm10k_sbus *sb; + int error; + + FM10K_SW_TRACE("sbus %s: attaching", name); + + sb = (struct fm10k_sbus *)rte_zmalloc + ("fm10k_sbus", sizeof(struct fm10k_sbus), 0); + if (sb == NULL) { + FM10K_SW_INFO("sbus %s: failed to allocate context", name); + goto fail; + } + + sb->sw = sw; + sb->name = name; + pthread_mutex_init(&sb->lock, NULL); + + sb->cfg_reg = cfg_reg; + sb->cmd_reg = cfg_reg + FM10K_SW_REG_OFF(1); + sb->req_reg = cfg_reg + FM10K_SW_REG_OFF(2); + sb->resp_reg = cfg_reg + FM10K_SW_REG_OFF(3); + + error = fm10k_sbus_init(sb); + if (error) + goto fail; + + FM10K_SW_TRACE("sbus %s: attach successful", name); + return sb; +fail: + if (sb) + fm10k_sbus_detach(sb); + return NULL; +} + +void +fm10k_sbus_detach(struct fm10k_sbus *sb) +{ + FM10K_SW_TRACE("sbus %s: detaching", sb->name); + + rte_free(sb); +} + +static int +fm10k_sbus_init(struct fm10k_sbus *sb) +{ + uint32_t data; + int error; + + error = fm10k_sbus_sbm_reset(sb); + if (error) + goto done; + + error = fm10k_sbus_reset_all(sb); + if (error) + goto done; + + /* set clock to REFCLK/2 */ + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SBUS_CONTROLLER, 0x0a, + FM10K_SW_SBUS_RING_DIVIDER); + if (error) { + FM10K_SW_ERR("sbus %s: failed to set ring divider", sb->name); + goto done; + } + + error = fm10k_sbus_read(sb, FM10K_SW_SBUS_ADDR_SBUS_CONTROLLER, 0x0a, + &data); + if (error) { + FM10K_SW_ERR("sbus %s: failed to read back ring divider", + sb->name); + goto done; + } + if (data != FM10K_SW_SBUS_RING_DIVIDER) { + FM10K_SW_ERR("sbus %s: ring divider " + "verify failed (expected %u, got %u)", + sb->name, FM10K_SW_SBUS_RING_DIVIDER, data); + error = -1; + goto done; + } + +done: + return error; +} + +static int +fm10k_sbus_exec(struct fm10k_sbus *sb, struct fm10k_sbus_req *req) +{ + struct fm10k_switch *sw = sb->sw; + unsigned int total_usecs; + unsigned int drop_lock; + unsigned int delay_time; + int error = 0; + uint32_t data; + uint8_t expected_result; + + FM10K_SW_SBUS_LOCK(sb); + + FM10K_SW_SWITCH_LOCK(sw); + data = fm10k_read_switch_reg(sw, sb->cmd_reg); + if (data & FM10K_SW_SBUS_COMMAND_BUSY) { + FM10K_SW_INFO("sbus %s: bus busy (0x%08x)", + sb->name, data); + error = -1; + goto done; + } + + switch (req->op) { + case FM10K_SW_SBUS_OP_RESET: + FM10K_SW_TRACE("sbus %s: RESET dev=0x%02x reg=0x%02x data=0x%08x", + sb->name, req->dev, req->reg, req->data); + expected_result = FM10K_SW_SBUS_RESULT_RESET; + fm10k_write_switch_reg(sw, sb->req_reg, req->data); + break; + case FM10K_SW_SBUS_OP_WRITE: + FM10K_SW_TRACE("sbus %s: WRITE dev=0x%02x reg=0x%02x data=0x%08x", + sb->name, req->dev, req->reg, req->data); + expected_result = FM10K_SW_SBUS_RESULT_WRITE; + fm10k_write_switch_reg(sw, sb->req_reg, req->data); + break; + case FM10K_SW_SBUS_OP_READ: + FM10K_SW_TRACE("sbus %s: READ dev=0x%02x reg=0x%02x", + sb->name, req->dev, req->reg); + expected_result = FM10K_SW_SBUS_RESULT_READ; + req->data = 0; + break; + default: + FM10K_SW_INFO("sbus %s: invalid opcode 0x%02x", + sb->name, req->op); + error = -1; + goto done; + } + + /* Clear the execute bit */ + fm10k_write_switch_reg(sw, sb->cmd_reg, 0); + + data = + FM10K_SW_MAKE_REG_FIELD(SBUS_COMMAND_OP, req->op) | + FM10K_SW_MAKE_REG_FIELD(SBUS_COMMAND_ADDRESS, req->dev) | + FM10K_SW_MAKE_REG_FIELD(SBUS_COMMAND_REGISTER, req->reg) | + FM10K_SW_SBUS_COMMAND_EXECUTE; + fm10k_write_switch_reg(sw, sb->cmd_reg, data); + fm10k_write_flush(sw); + + total_usecs = 0; + delay_time = 1; + drop_lock = 0; + do { + if (drop_lock) + FM10K_SW_SWITCH_UNLOCK(sw); + fm10k_udelay(delay_time); + if (drop_lock) + FM10K_SW_SWITCH_LOCK(sw); + total_usecs += delay_time; + if (total_usecs >= FM10K_SW_SBUS_COMMAND_WAIT_LOCK_US_MAX) { + drop_lock = 1; + delay_time <<= 1; + } + + data = fm10k_read_switch_reg(sw, sb->cmd_reg); + if (!(data & FM10K_SW_SBUS_COMMAND_BUSY)) { + if (FM10K_SW_REG_FIELD(data, + SBUS_COMMAND_RESULT_CODE) + != expected_result) { + FM10K_SW_INFO("sbus %s: expected " + "result code %u, got %u", sb->name, + expected_result, + FM10K_SW_REG_FIELD(data, + SBUS_COMMAND_RESULT_CODE)); + error = -1; + goto done; + } + if (req->op == FM10K_SW_SBUS_OP_READ) { + req->data = + fm10k_read_switch_reg(sw, sb->resp_reg); + FM10K_SW_TRACE("sbus %s: READ data=0x%02x", + sb->name, req->data); + } + goto done; + } + + } while (total_usecs < FM10K_SW_SBUS_COMMAND_TIMEOUT_US); + + error = -1; + FM10K_SW_INFO("sbus %s: command timed out after %u us " + "(op=0x%02x dev=0x%02x reg=0x%02x data=0x%08x)", sb->name, + total_usecs, req->op, req->dev, req->reg, req->data); + +done: + FM10K_SW_SWITCH_UNLOCK(sw); + FM10K_SW_SBUS_UNLOCK(sb); + return error; +} + +static int +fm10k_sbus_reset_all(struct fm10k_sbus *sb) +{ + struct fm10k_sbus_req req; + int error; + + req.op = FM10K_SW_SBUS_OP_RESET; + req.dev = FM10K_SW_SBUS_ADDR_BROADCAST; + req.reg = 0; + req.data = 0; + + error = fm10k_sbus_exec(sb, &req); + + FM10K_SW_TRACE("sbus %s: broadcast reset %s (%d)", sb->name, + error ? "failed" : "succeeded", error); + + return error; +} + +static int +fm10k_sbus_sbm_reset(struct fm10k_sbus *sb) +{ + struct fm10k_sbus_req req; + int error; + + req.op = FM10K_SW_SBUS_OP_RESET; + req.dev = FM10K_SW_SBUS_ADDR_SPICO; + req.reg = 0; + req.data = 0; + + error = fm10k_sbus_exec(sb, &req); + + FM10K_SW_TRACE("sbus %s: SBM reset %s (%d)", sb->name, + error ? "failed" : "succeeded", error); + + return error; +} + +int +fm10k_sbus_read(struct fm10k_sbus *sb, uint8_t dev, uint8_t reg, uint32_t *data) +{ + struct fm10k_sbus_req req; + int error; + + req.op = FM10K_SW_SBUS_OP_READ; + req.dev = dev; + req.reg = reg; + + error = fm10k_sbus_exec(sb, &req); + *data = error ? 0 : req.data; + + return error; +} + +int +fm10k_sbus_write(struct fm10k_sbus *sb, uint8_t dev, uint8_t reg, uint32_t data) +{ + struct fm10k_sbus_req req; + int error; + + req.op = FM10K_SW_SBUS_OP_WRITE; + req.dev = dev; + req.reg = reg; + req.data = data; + + error = fm10k_sbus_exec(sb, &req); + + return error; +} diff --git a/drivers/net/fm10k/switch/fm10k_sbus.h b/drivers/net/fm10k/switch/fm10k_sbus.h new file mode 100644 index 0000000..e67967f --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_sbus.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#ifndef _FM10K_SW_SBUS_H_ +#define _FM10K_SW_SBUS_H_ + +#include + + +struct fm10k_sbus { + struct fm10k_switch *sw; + const char *name; + pthread_mutex_t lock; + unsigned int cfg_reg; + unsigned int cmd_reg; + unsigned int req_reg; + unsigned int resp_reg; +}; + +#define FM10K_SW_SBUS_LOCK(sb_) pthread_mutex_lock(&((sb_)->lock)) +#define FM10K_SW_SBUS_UNLOCK(sb_) pthread_mutex_unlock(&((sb_)->lock)) + +struct fm10k_sbus_req { + uint8_t op; + uint8_t dev; + uint8_t reg; + uint32_t data; +}; + + +struct fm10k_sbus *fm10k_sbus_attach(struct fm10k_switch *sw, + const char *name, unsigned int cfg_reg); +void fm10k_sbus_detach(struct fm10k_sbus *sb); +int fm10k_sbus_read(struct fm10k_sbus *sb, + uint8_t dev, uint8_t reg, uint32_t *data); +int fm10k_sbus_write(struct fm10k_sbus *sb, + uint8_t dev, uint8_t reg, uint32_t data); + +#endif /* _FM10K_SW_SBUS_H_ */ diff --git a/drivers/net/fm10k/switch/fm10k_switch.h b/drivers/net/fm10k/switch/fm10k_switch.h new file mode 100644 index 0000000..d69b51c --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_switch.h @@ -0,0 +1,336 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#ifndef _FM10K_SW_SWITCH_H_ +#define _FM10K_SW_SWITCH_H_ + +#include +#include +#include +#include + +#include "../fm10k.h" +#include "fm10k_debug.h" +#include "fm10k_regs.h" + + +/* + * EPL + */ +#define FM10K_SW_EXT_PORTS_MAX 4 + +#define FM10K_SW_EPLS_MAX 9 +#define FM10K_SW_EPLS_SUPPORTED 2 +#define FM10K_SW_EPL_LANES 4 +#define FM10K_SW_EPLS_PEP_MAX 2 + +/* + * PEP + */ +#define FM10K_SW_PEP_GROUP_MAX 10 +#define FM10K_SW_LOGICAL_PORTS_MAX 48 + +#define FM10K_SW_PEPS_MAX 9 +#define FM10K_SW_PEPS_SUPPORTED 4 +#define FM10K_SW_PEP_PORTS_MAX 4 + +/* + * GLORT + */ +#define FM10K_SW_GROUP_MAX 10 +#define FM10K_SW_VFS_MAX 64 +#define FM10K_SW_PFS_GLORT_START 0x1000 +#define FM10K_SW_VF_GLORT_START 0x2000 +#define FM10K_SW_MULTI_GLORT_START 0x3000 +#define FM10K_SW_DPORT_MASK(lport) (1ULL << (lport)) + + +/* + * CONFIG + */ +#define FM10K_SW_CONFIG_MAX 1000 +#define FM10K_SW_FFU_RULE_MAX 256 +#define FM10K_SW_FFU_RULE_ITEM_MAX 10 + +/* + * FFU COUNT + */ +#define FM10K_SW_FFU_CNT_BANK 3 +#define FM10K_SW_POLICER_LAST 19 +#define FM10K_SW_FFU_CNT_START (FM10K_SW_POLICER_LAST + 1) +#define FM10K_SW_FFU_CNT_MAX 100 + +#define FM10K_SW_PEP_QUEUES_MAX 256 +#define FM10K_SW_VF_QUEUES_MAX \ + (FM10K_SW_PEP_QUEUES_MAX - 1) /* Need 1 queue for PF */ + +#define FM10K_SW_FTAG_SIZE 8 +#define FM10K_SW_PACKET_SIZE_MIN 17 +#define FM10K_SW_PACKET_SIZE_MAX (15 * 1024) +#define FM10K_SW_MTU_MAX \ + (FM10K_SW_PACKET_SIZE_MAX - ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN) +#define FM10K_SW_SEG_SIZE_MAX (16 * 1024) +#define FM10K_SW_TSO_SIZE_MAX (256 * 1024 - 1) + +#define FM10K_SW_MEM_POOL_SEG_SIZE 192 +#define FM10K_SW_MEM_POOL_SEGS_MAX 24576 +#define FM10K_SW_MEM_POOL_SEGS_RSVD 256 + + + +#define FM10K_SW_CARD_ID(v_, d_) (((v_) << 16) | (d_)) +#define FM10K_SW_CARD(vname_, dname_) \ + FM10K_SW_CARD_ID(FM10K_SW_VENDOR_ID_##vname_, \ + FM10K_SW_DEV_ID_##dname_) + +/* + * All IDs that may appear in the vendor ID or subsystem vendor ID. + */ +#define FM10K_SW_VENDOR_ID_INTEL 0x8086 +#define FM10K_SW_VENDOR_ID_SILICOM 0x1374 +#define FM10K_SW_VENDOR_ID_SILICOM_RB 0x1B2E + + +/* + * All IDs that may appear in the device ID or subsystem device ID. + */ +#define FM10K_SW_DEV_ID_FM10K 0x15a4 + +/* Silicom cards */ +#define FM10K_SW_DEV_ID_PE310G4DBIR_T 0x01B0 +#define FM10K_SW_DEV_ID_PE310G4DBIR_SRD 0x01B1 +#define FM10K_SW_DEV_ID_PE310G4DBIR_LRD 0x01B2 +#define FM10K_SW_DEV_ID_PE310G4DBIR_ER 0x01B3 +#define FM10K_SW_DEV_ID_PE310G4DBIR_DA 0x01B4 +#define FM10K_SW_DEV_ID_PE340G2DBIR_QS41 0x01B8 +#define FM10K_SW_DEV_ID_PE340G2DBIR_QS43 0x01B9 +#define FM10K_SW_DEV_ID_PE340G2DBIR_QL4 0x01BA +#define FM10K_SW_DEV_ID_PE3100G2DQIR_QXSL4 0x01C0 +#define FM10K_SW_DEV_ID_PE3100G2DQIR_QXSL4_REV_2 0x01C4 +#define FM10K_SW_DEV_ID_PE3100G2DQIRL_QXSL4 0x01C1 +#define FM10K_SW_DEV_ID_PE3100G2DQIRM_QXSL4 0x01C2 +#define FM10K_SW_DEV_ID_PE325G2DSIR 0x01C8 + +/* + * SWITCH + */ + +struct fm10k_device_info { + uint16_t subvendor; + uint16_t subdevice; + const char *desc; + uint8_t num_ext_ports; + uint8_t ext_port_speed; + uint8_t num_epls; + uint8_t num_peps; +}; + + +struct fm10k_i2c; +struct fm10k_sbus; +struct fm10k_hw; +struct fm10k_ext_ports; +struct fm10k_dpdk_cfg; + +struct fm10k_sw_port_map { + uint32_t glort; + uint16_t logical_port; /* logical port number */ + uint16_t physical_port; /* */ +}; + +struct fm10k_switch { + uint32_t *hw_addr; + uint32_t *sw_addr; + struct fm10k_hw *master_hw; + struct fm10k_device_info *info; + pthread_mutex_t lock; + struct fm10k_i2c *i2c; + struct fm10k_sbus *epl_sbus; + struct fm10k_ext_ports *ext_ports; + sem_t intr_tq; + pthread_t intr_task; + pthread_t led_task; + pthread_t stats_task; + uint32_t detaching; + uint32_t glort_cam_ram_idx; + uint32_t glort_dest_table_idx; + uint32_t mcast_dest_table_idx; + uint32_t mcast_len_table_idx; + uint32_t mcast_vlan_table_idx; + uint32_t epl_serdes_code_version_build_id; + uint16_t pep_mask; /* mask of non-master peps */ + uint8_t pepno; + uint8_t serdes_loopback; + uint8_t epla_no; + uint8_t eplb_no; + uint8_t mac_addr[6]; + struct fm10k_dpdk_cfg *dpdk_cfg; + struct fm10k_sw_port_map *pep_map; + struct fm10k_sw_port_map *epl_map; + int inited; +}; + +#define FM10K_SW_SWITCH_LOCK(sw_) pthread_mutex_lock(&((sw_)->lock)) +#define FM10K_SW_SWITCH_UNLOCK(sw_) pthread_mutex_unlock(&((sw_)->lock)) + +#define FM10K_SW_HOWMANY(x, y, y1) (((x) + (y) - 1) / (y1)) + + +static inline uint64_t +fm10k_uptime_us(void) +{ + struct timeval tv; + + gettimeofday(&tv, NULL); + return ((uint64_t)tv.tv_sec * 1000000 + tv.tv_usec); +} + + +static inline uint32_t +fm10k_read_switch_reg(struct fm10k_switch *sw, uint32_t reg) +{ + return ((volatile uint32_t *)sw->master_hw->sw_addr)[reg]; +} + +static inline uint64_t +fm10k_read_switch_reg64(struct fm10k_switch *sw, uint32_t reg) +{ + uint64_t temp, result; + + result = ((volatile uint32_t *)sw->master_hw->sw_addr)[reg]; + temp = ((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 1]; + result |= temp << 32; + + return result; +} + +static inline void +fm10k_read_switch_array(struct fm10k_switch *sw, + uint32_t reg, uint32_t *results, uint32_t count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + results[i] = + ((volatile uint32_t *)sw->master_hw->sw_addr)[reg + i]; +} + + +static inline void +fm10k_write_switch_reg(struct fm10k_switch *sw, uint32_t reg, uint32_t val) +{ + ((volatile uint32_t *)sw->master_hw->sw_addr)[reg] = val; +} + +static inline void +fm10k_write_switch_reg64(struct fm10k_switch *sw, uint32_t reg, uint64_t val) +{ + ((volatile uint32_t *)sw->master_hw->sw_addr)[reg] = val & 0xffffffff; + ((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 1] = val >> 32; +} + +static inline void +fm10k_write_switch_reg128(struct fm10k_switch *sw, + uint32_t reg, uint64_t val_hi, uint64_t val_lo) +{ + ((volatile uint32_t *)sw->master_hw->sw_addr)[reg] = + val_lo & 0xffffffff; + ((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 1] = + val_lo >> 32; + ((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 2] = + val_hi & 0xffffffff; + ((volatile uint32_t *)sw->master_hw->sw_addr)[reg + 3] = + val_hi >> 32; +} + +static inline void +fm10k_write_switch_array(struct fm10k_switch *sw, + uint32_t reg, uint32_t *data, uint32_t count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + ((volatile uint32_t *)sw->master_hw->sw_addr)[reg + i] = + data[i]; +} + +static inline uint32_t +fm10k_write_flush(struct fm10k_switch *sw) +{ + return ((volatile uint32_t *)sw->master_hw->hw_addr)[FM10K_SW_CTRL]; +} + +static inline void +fm10k_gpio_output_set(struct fm10k_switch *sw, int gpio_pin, int value) +{ + uint32_t data; + + data = fm10k_read_switch_reg(sw, FM10K_SW_GPIO_CFG); + data |= 1 << gpio_pin; + data &= ~(1 << (gpio_pin + 16)); + + /* set gpio output */ + fm10k_write_switch_reg(sw, FM10K_SW_GPIO_CFG, data); + + /* + * Wait 1 msec (PCA spec specifies reset pulse width = 4 ns and + * and reset time = 100 ns) + */ + usec_delay(1000); + /* set reset */ + data = fm10k_read_switch_reg(sw, FM10K_SW_GPIO_DATA); + if (value == 0) + data &= ~(1 << gpio_pin); + else + data |= 1 << gpio_pin; + + fm10k_write_switch_reg(sw, FM10K_SW_GPIO_DATA, data); +} + +#define fm10k_udelay usec_delay +typedef int eth_fm10k_dev_init_half_func(struct fm10k_hw *hw); + +unsigned int fm10k_switch_eplidx_to_eplno + (struct fm10k_switch *sw, unsigned int eplidx); +void fm10k_switch_intr(struct fm10k_hw *hw); + +struct fm10k_switch *fm10k_switch_get(void); +struct fm10k_device_info *fm10k_get_device_info(struct fm10k_hw *hw); +int fm10k_switch_dpdk_port_start(struct fm10k_hw *hw, void *rte_dev, + uint8_t is_pf, bool master, eth_fm10k_dev_init_half_func *func); +void fm10k_switch_dpdk_port_stop(struct fm10k_hw *hw); +int fm10k_switch_dpdk_hw_queue_map(struct fm10k_hw *hw, + uint16_t queue, uint16_t max_queue, + struct fm10k_hw **map_hw, uint16_t *map_queue); +int fm10k_switch_dpdk_mapped_hw_get(struct fm10k_hw *hw, + struct fm10k_hw *hw_list[]); +int fm10k_switch_dpdk_pf_no_get(struct fm10k_hw *hw); +int fm10k_switch_dpdk_port_no_get(struct fm10k_hw *hw); +void *fm10k_switch_dpdk_port_rte_dev_get(struct fm10k_hw *hw); +struct fm10k_flow_list * +fm10k_switch_dpdk_port_flow_list_get(struct fm10k_hw *hw); +void fm10k_switch_dpdk_tx_queue_num_set(struct fm10k_hw *hw, uint8_t num); +void fm10k_switch_dpdk_rx_queue_num_set(struct fm10k_hw *hw, uint8_t num); + +uint32_t fm10k_switch_pf_logical_get(uint8_t pf_no); +uint32_t fm10k_switch_epl_logical_get(uint8_t epl_no); +uint32_t fm10k_switch_vf_glort_get(uint8_t vf_no); +uint32_t fm10k_switch_pf_glort_get(uint8_t pf_no); +uint32_t fm10k_switch_pfs_glort_get(uint8_t pf1, uint8_t pf2); +uint32_t fm10k_switch_epl_glort_get(uint8_t epl_no); +uint32_t fm10k_switch_multi_glort_get(uint8_t pf1, uint8_t pf2, + uint16_t vlan1, uint16_t vlan2, bool *p_new); + +int fm10k_switch_mirror_set(struct fm10k_hw *hw, u16 dest_port, u16 vlan); +int fm10k_switch_mirror_reset(struct fm10k_hw *hw); + +void fm10k_switch_flowset_switchto(const char *name); +void fm10k_switch_show_port(void); +void fm10k_switch_show_ffu(void); +void fm10k_switch_show_bank(void); + +void fm10k_flow_list_init(void *flow_list); +const struct rte_flow_ops *fm10k_flow_ops_get(void); + +#endif