[3/3] net/i40e/base: add constants for PTP pins
diff mbox series

Message ID 20200325032356.20198-4-jiaqix.min@intel.com
State New
Delegated to: xiaolong ye
Headers show
Series
  • update i40e base code
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Context Check Description
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Jiaqi Min March 25, 2020, 3:23 a.m. UTC
Introduce constants for handling PTP pins used for external
clock source.

Signed-off-by: Piotr Kwapulinski <piotr.kwapulinski@intel.com>
Signed-off-by: Jiaqi Min <jiaqix.min@intel.com>
---
 drivers/net/i40e/base/i40e_register.h | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Kwapulinski, Piotr March 25, 2020, 10:03 a.m. UTC | #1
ACK

-----Original Message-----
From: Min, JiaqiX <jiaqix.min@intel.com> 
Sent: Wednesday, March 25, 2020 4:24 AM
To: dev@dpdk.org
Cc: Min, JiaqiX <jiaqix.min@intel.com>; Kwapulinski, Piotr <piotr.kwapulinski@intel.com>
Subject: [PATCH 3/3] net/i40e/base: add constants for PTP pins

Introduce constants for handling PTP pins used for external clock source.

Signed-off-by: Piotr Kwapulinski <piotr.kwapulinski@intel.com>
Signed-off-by: Jiaqi Min <jiaqix.min@intel.com>
---
 drivers/net/i40e/base/i40e_register.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h
index 436f48efa..dffcc633c 100644
--- a/drivers/net/i40e/base/i40e_register.h
+++ b/drivers/net/i40e/base/i40e_register.h
@@ -2910,6 +2910,10 @@
 #define I40E_PRTTSYN_AUX_0_PULSEW_MASK   I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
 #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16  #define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK  I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
+#define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17 #define 
+I40E_PRTTSYN_AUX_0_PTPFLAG_MASK \
+		I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT) #define 
+I40E_PRTTSYN_AUX_0_PTP_OUT_SYNC_CLK_IO 0xF
 #define I40E_PRTTSYN_AUX_1(_i)               (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_AUX_1_MAX_INDEX         1
 #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT      0
--
2.17.1

--------------------------------------------------------------------

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Patch
diff mbox series

diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h
index 436f48efa..dffcc633c 100644
--- a/drivers/net/i40e/base/i40e_register.h
+++ b/drivers/net/i40e/base/i40e_register.h
@@ -2910,6 +2910,10 @@ 
 #define I40E_PRTTSYN_AUX_0_PULSEW_MASK   I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
 #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16
 #define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK  I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
+#define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17
+#define I40E_PRTTSYN_AUX_0_PTPFLAG_MASK \
+		I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT)
+#define I40E_PRTTSYN_AUX_0_PTP_OUT_SYNC_CLK_IO 0xF
 #define I40E_PRTTSYN_AUX_1(_i)               (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
 #define I40E_PRTTSYN_AUX_1_MAX_INDEX         1
 #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT      0