From patchwork Wed Mar 25 03:23:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Min, JiaqiX" X-Patchwork-Id: 67094 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A47C8A058E; Wed, 25 Mar 2020 04:25:43 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0C5ED1C065; Wed, 25 Mar 2020 04:25:27 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id BB2BD1BFE2 for ; Wed, 25 Mar 2020 04:25:23 +0100 (CET) IronPort-SDR: jN7z36vesH/uLZMOY0SJhoyE+IeaeWh8bCRQPuvoAYplkZ5zup+KC2hK9vxOyCHCjEqpgnzY9J 1hRtGg5DEccA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2020 20:25:23 -0700 IronPort-SDR: egKN5zC9MH26kUSOffAqeK9wWGzxBUw9bVikABNMIa6bYLYHeg7FUB0KZPvAJLXNY5vrcGeJM9 Y9zXbhXmp9dQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,302,1580803200"; d="scan'208";a="265396789" Received: from dpdk.sh.intel.com ([10.239.255.20]) by orsmga002.jf.intel.com with ESMTP; 24 Mar 2020 20:25:21 -0700 From: Jiaqi Min To: dev@dpdk.org Cc: Jiaqi Min , Piotr Kwapulinski Date: Wed, 25 Mar 2020 03:23:56 +0000 Message-Id: <20200325032356.20198-4-jiaqix.min@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200325032356.20198-1-jiaqix.min@intel.com> References: <20200325032356.20198-1-jiaqix.min@intel.com> Subject: [dpdk-dev] [PATCH 3/3] net/i40e/base: add constants for PTP pins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Introduce constants for handling PTP pins used for external clock source. Signed-off-by: Piotr Kwapulinski Signed-off-by: Jiaqi Min Signed-off-by: Piotr Kwapulinski Signed-off-by: Jiaqi Min --- drivers/net/i40e/base/i40e_register.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h index 436f48efa..dffcc633c 100644 --- a/drivers/net/i40e/base/i40e_register.h +++ b/drivers/net/i40e/base/i40e_register.h @@ -2910,6 +2910,10 @@ #define I40E_PRTTSYN_AUX_0_PULSEW_MASK I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT) #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16 #define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT) +#define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17 +#define I40E_PRTTSYN_AUX_0_PTPFLAG_MASK \ + I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT) +#define I40E_PRTTSYN_AUX_0_PTP_OUT_SYNC_CLK_IO 0xF #define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ #define I40E_PRTTSYN_AUX_1_MAX_INDEX 1 #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0