diff mbox series

[02/52] net/ice/base: add FDIR program status WB macro

Message ID	20200603024016.30636-3-qi.z.zhang@intel.com (mailing list archive)
State	Superseded, archived
Delegated to:	xiaolong ye
Headers	IronPort-SDR: bYyqOLDSVLEAMQMIprAtPrIoiYHA9kwoYzPZHUmI6+xz6T59CSOl5BevN37Ssl2QLwkJPUrL8f MtIpREXcv9lQ== IronPort-SDR: 7n9sWgF2PjEcCC7WYZ6k2L43C4Qxr//bgs3omRiViDBicW/4jGLwvE0sCt76hBns/aB0eLqVSI 7DRvKviBcKoA== From: Qi Zhang <qi.z.zhang@intel.com> To: qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>, Yahui Cao <yahui.cao@intel.com>, "Paul M . Stillwell Jr" <paul.m.stillwell.jr@intel.com> Date: Wed, 3 Jun 2020 10:39:26 +0800 Message-Id: <20200603024016.30636-3-qi.z.zhang@intel.com> In-Reply-To: <20200603024016.30636-1-qi.z.zhang@intel.com> References: <20200603024016.30636-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 02/52] net/ice/base: add FDIR program status WB macro Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	net/ice: base code update \| [00/52] net/ice: base code update [01/52] net/ice/base: add support for non-IP Layer2 protocol [02/52] net/ice/base: add FDIR program status WB macro [03/52] net/ice/base: disable profile merge for FDIR [04/52] net/ice/base: avoid undefined behavior [05/52] net/ice/base: consolidate implementation of MAC config set [06/52] net/ice/base: report AOC PHY Types as Fiber [07/52] net/ice/base: gate devices from FW link override [08/52] net/ice/base: improve VSI filters rebuild [09/52] net/ice/base: add AUI media type [10/52] net/ice/base: fix variable type for ACL [11/52] net/ice/base: update PHY type high max index value [12/52] net/ice/base: consolidate VF Promiscuous mode [13/52] net/ice/base: refactor flow director filter swap [14/52] net/ice/base: change IPV6 training packet [15/52] net/ice/base: group function protoypes together [16/52] net/ice/base: cleanup comment formatting [17/52] net/ice/base: add FDIR support for L2TPV3 ESP AH and PFCP [18/52] net/ice/base: add FD completion report option [19/52] net/ice/base: initialize Set PHY Configuration FEC fields [20/52] net/ice/baes: add NVM help functions [21/52] net/ice/base: allow GENEVE and VXLAN rules with VLAN [22/52] net/ice/base: increase timeout after PFR [23/52] net/ice/base: remove unnecessary braces [24/52] net/ice/base: adjust function signature style format [25/52] net/ice/base: add RSS support for IPv6 prefix [26/52] net/ice/base: use macro for sizeof [27/52] net/ice/base: add debug logs [28/52] net/ice/base: return correct error code [29/52] net/ice/base: remove unnecessary code [30/52] net/ice/base: add support for more PPPoE packet type [31/52] net/ice/base: reset flags when all rules are deleted [32/52] net/ice/base: reset capabilities before parsing [33/52] net/ice/base: add RL profile bit mask check [34/52] net/ice/base: update the vsi handle to remaining VSI [35/52] net/ice/base: correct return value [36/52] net/ice/base: remove unneeded variable [37/52] net/ice/base: fix for memory leak [38/52] net/ice/base: add entries in Profile TCAM with priority [39/52] net/ice/base: remove unimplemented function prototypes [40/52] net/ice/base: add new API to check all autoneg enable bits [41/52] net/ice/base: avoid PPPoE ipv4 overlap [42/52] net/ice/base: initialize AQ failure variable when set fc [43/52] net/ice/base: adjust scheduler default BW weight [44/52] net/ice/base: distribute Tx queues evenly [45/52] net/ice/base: add a new command to LLDP commands [46/52] net/ice/base: remove unused code for VSI list free [47/52] net/ice/base: fix reference count when update VSI list [48/52] net/ice/base: add more tunnel type for IPv4 and IPv6 [49/52] net/ice/base: fix uninitialized flag [50/52] net/ice/base: add more device ID support [51/52] net/ice/base: add 1G SGMII PHY type [52/52] net/ice/base: update IPV4 and IPV6 flow ptype masks

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK
ci/Intel-compilation	success	Compilation OK

Commit Message

Qi Zhang June 3, 2020, 2:39 a.m. UTC

  Add descriptor field offset and mask definition. It is used to parse
FDIR rx descriptor field value.

Signed-off-by: Yahui Cao <yahui.cao@intel.com>
Signed-off-by: Paul M. Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_lan_tx_rx.h | 44 ++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff mbox series

Patch

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index a0e284a8d..99edcc8ae 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -175,6 +175,50 @@  struct ice_fltr_desc {
 			(0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
 #define ICE_FXD_FLTR_QW1_FDID_ZERO	0x0ULL
 
+/* definition for FD filter programming status descriptor WB format */
+#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S	28
+#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_M	\
+			(0xFULL << ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S)
+
+#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S	32
+#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_M	\
+			(0xFFFFFFFFULL << ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S)
+
+#define ICE_FXD_FLTR_WB_QW1_DD_S	0
+#define ICE_FXD_FLTR_WB_QW1_DD_M	(0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S)
+#define ICE_FXD_FLTR_WB_QW1_DD_YES	0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_PROG_ID_S	1
+#define ICE_FXD_FLTR_WB_QW1_PROG_ID_M	\
+				(0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S)
+#define ICE_FXD_FLTR_WB_QW1_PROG_ADD	0x0ULL
+#define ICE_FXD_FLTR_WB_QW1_PROG_DEL	0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_FAIL_S	4
+#define ICE_FXD_FLTR_WB_QW1_FAIL_M	(0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S)
+#define ICE_FXD_FLTR_WB_QW1_FAIL_YES	0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S	5
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M	\
+				(0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES	0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S	8
+#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_M	\
+				(0x3FFFULL << ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S)
+
+#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_S	28
+#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_M	\
+				(0x7FULL << ICE_FXD_FLTR_WB_QW1_PKT_PROF_S)
+
+#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S	38
+#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_M	\
+				(0x3FFFFFF << ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S)
+
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M	\
+				(0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES	0x1ULL
+
 enum ice_rx_desc_status_bits {
 	/* Note: These are predefined bit offsets */
 	ICE_RX_DESC_STATUS_DD_S			= 0,