Change-Id: I7fc0656b531dded6a95fbb0777c3b0dd5209ba61
Signed-off-by: McDaniel, Timothy <timothy.mcdaniel@intel.com>
---
config/common_base | 17 +++++++++++++++++
config/rte_config.h | 6 ++++++
drivers/event/Makefile | 5 +++++
drivers/event/dlb/Makefile | 36 ++++++++++++++++++++++++++++++++++++
drivers/event/dlb/meson.build | 16 ++++++++++++++++
drivers/event/meson.build | 3 +++
6 files changed, 83 insertions(+)
create mode 100644 drivers/event/dlb/Makefile
create mode 100644 drivers/event/dlb/meson.build
@@ -789,6 +789,23 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n
CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n
#
+# Compile PMD for dlb event device
+#
+CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV=y
+# Specify an upper bound on cycles between each CQ access when hard polling
+CONFIG_RTE_LIBRTE_PMD_DLB_POLL_INTERVAL=1000
+# Specify control state to use when executing UMWAIT instruction.
+# If 0, then use CO.2, which has a slower wakeup time, but greater
+# power savings.
+# If 1, then use C0.1, which has a faster wakeup time, but smaller
+# power savings.
+CONFIG_RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE=0
+# Suppress statistics calculation
+CONFIG_RTE_LIBRTE_PMD_DLB_QUELL_STATS=n
+# Specify software credit quanta
+CONFIG_RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA=32
+
+#
# Compile raw device support
# EXPERIMENTAL: API may change without prior notice
#
@@ -133,4 +133,10 @@
/* QEDE PMD defines */
#define RTE_LIBRTE_QEDE_FW ""
+/* DLB PMD defines */
+#define RTE_LIBRTE_PMD_DLB_POLL_INTERVAL 1000
+#define RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE 0
+#undef RTE_LIBRTE_PMD_DLB_QUELL_STATS
+#define RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA 32
+
#endif /* _RTE_CONFIG_H_ */
@@ -16,5 +16,10 @@ ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)
DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += dpaa2
endif
DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPDL_EVENTDEV) += opdl
+# DLB limited to x86 architectures
+ifneq ($(filter y,$(CONFIG_RTE_ARCH_X86_64) \
+ $(CONFIG_RTE_ARCH_X86)),)
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV) += dlb
+endif
include $(RTE_SDK)/mk/rte.subdir.mk
new file mode 100644
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2016-2020 Intel Corporation.
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_dlb_eventdev.a
+
+# build flags
+CFLAGS += -O3 -pthread
+CFLAGS += $(WERROR_FLAGS)
+# rte_mp_ APIs are still marked experimental
+CFLAGS += -DALLOW_EXPERIMENTAL_API
+LDLIBS += -lrte_eal -lrte_eventdev -lrte_mbuf -lrte_kvargs -lrte_ring
+LDLIBS += -lrte_mempool -lpthread -lrte_pci -lrte_bus_pci
+
+# library version
+LIBABIVER := 1
+
+# versioning export map
+EXPORT_MAP := rte_pmd_dlb_event_version.map
+
+# library source files
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV) += dlb.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV) += dlb_iface.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV) += dlb_xstats.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV) += rte_pmd_dlb.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV) += dlb_selftest.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV) += pf/dlb_pf.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV) += pf/dlb_main.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_DLB_EVENTDEV) += pf/base/dlb_resource.c
+
+# export include files
+SYMLINK-y-include += rte_pmd_dlb.h
+
+include $(RTE_SDK)/mk/rte.lib.mk
new file mode 100644
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019-2020 Intel Corporation
+
+sources = files('dlb.c',
+ 'dlb_iface.c',
+ 'dlb_xstats.c',
+ 'rte_pmd_dlb.c',
+ 'dlb_selftest.c',
+ 'pf/dlb_pf.c',
+ 'pf/dlb_main.c',
+ 'pf/base/dlb_resource.c'
+)
+
+allow_experimental_apis = true
+deps += ['mbuf', 'mempool', 'ring', 'pci', 'bus_pci']
+install_headers('rte_pmd_dlb.h')
@@ -6,6 +6,9 @@ if not (toolchain == 'gcc' and cc.version().version_compare('<4.8.6') and
dpdk_conf.has('RTE_ARCH_ARM64'))
drivers += 'octeontx'
endif
+if dpdk_conf.has('RTE_ARCH_X86_64') or dpdk_conf.has('RTE_ARCH_X86')
+ drivers += 'dlb'
+endif
std_deps = ['eventdev', 'kvargs']
config_flag_fmt = 'RTE_LIBRTE_@0@_EVENTDEV_PMD'
driver_name_fmt = 'rte_pmd_@0@_event'