This patch defines various PCI config space access APIs
in order to read and find IOV specific PCI capabilities.
With these definitions implemented, it enables the base
driver to do SR-IOV specific initialization and HW specific
configuration required from PF-PMD driver instance.
Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
drivers/net/qede/base/bcm_osal.h | 18 +++++++++++++-----
drivers/net/qede/base/ecore.h | 3 +++
drivers/net/qede/qede_main.c | 1 +
3 files changed, 17 insertions(+), 5 deletions(-)
@@ -21,6 +21,11 @@
#include <rte_ether.h>
#include <rte_io.h>
#include <rte_version.h>
+#include <rte_bus_pci.h>
+#include <rte_pci_regs.h>
+
+#define PCICFG_VENDOR_ID_OFFSET PCI_VENDOR_ID
+#define PCICFG_DEVICE_ID_OFFSET PCI_DEVICE_ID
/* Forward declaration */
struct ecore_dev;
@@ -286,11 +291,14 @@ typedef struct osal_list_t {
OSAL_LIST_PUSH_HEAD(new_entry, list)
/* PCI config space */
-
-#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) nothing
-#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) nothing
-#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) nothing
-#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, pcie_id) 0
+#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) \
+ rte_pci_read_config((dev)->pci_dev, dst, 1, address)
+#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) \
+ rte_pci_read_config((dev)->pci_dev, dst, 2, address)
+#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) \
+ rte_pci_read_config((dev)->pci_dev, dst, 4, address)
+#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, cap) \
+ rte_pci_find_next_ext_capability((dev)->pci_dev, cap)
#define OSAL_PCI_FIND_CAPABILITY(dev, pcie_id) 0
#define OSAL_PCI_WRITE_CONFIG_WORD(dev, address, val) nothing
#define OSAL_BAR_SIZE(dev, bar_id) 0
@@ -937,6 +937,9 @@ struct ecore_dev {
struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
struct ecore_dbg_params dbg_params;
osal_mutex_t dbg_lock;
+
+ /* DPDK specific ecore field */
+ struct rte_pci_device *pci_dev;
};
enum ecore_hsi_def_type {
@@ -37,6 +37,7 @@ static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev)
edev->regview = pci_dev->mem_resource[0].addr;
edev->doorbells = pci_dev->mem_resource[2].addr;
edev->db_size = pci_dev->mem_resource[2].len;
+ edev->pci_dev = pci_dev;
}
static int