diff mbox series

[v12,01/10] eal: introduce macro for bit definition

Message ID 20200727174715.330117-2-parav@mellanox.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series Improve mlx5 PMD driver framework for multiple classes |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail apply issues

Commit Message

Parav Pandit July 27, 2020, 5:47 p.m. UTC 
  There are several drivers which duplicate bit generation macro.
Introduce a generic bit macros so that such drivers avoid redefining
same in multiple drivers.

Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
---
Changelog:
v11->v12:
 - Define RTE_BIT32 macro as well
 - Use RTE_BIT32 and RTE_BIT64 macros in bitops as well
v4->v5:
 - Addressed comments from Morten Brørup
 - Renamed newly added macro to RTE_BIT64
 - Added doxygen comment section for the macro
v1->v2:
 - Addressed comments from Thomas and Gaten.
 - Avoided new file, added macro to rte_bitops.h
---
 lib/librte_eal/include/rte_bitops.h | 34 +++++++++++++++++++++--------
 1 file changed, 25 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/lib/librte_eal/include/rte_bitops.h b/lib/librte_eal/include/rte_bitops.h
index 740927f3b..141e8ea73 100644
--- a/lib/librte_eal/include/rte_bitops.h
+++ b/lib/librte_eal/include/rte_bitops.h
@@ -17,6 +17,22 @@ 
 #include <rte_debug.h>
 #include <rte_compat.h>
 
+/**
+ * Get the uint64_t value for a specified bit set.
+ *
+ * @param nr
+ *   The bit number in range of 0 to 63.
+ */
+#define RTE_BIT64(nr) (UINT64_C(1) << (nr))
+
+/**
+ * Get the uint32_t value for a specified bit set.
+ *
+ * @param nr
+ *   The bit number in range of 0 to 31.
+ */
+#define RTE_BIT32(nr) (UINT32_C(1) << (nr))
+
 /*------------------------ 32-bit relaxed operations ------------------------*/
 
 /**
@@ -59,7 +75,7 @@  rte_bit_relaxed_set32(unsigned int nr, volatile uint32_t *addr)
 {
 	RTE_ASSERT(nr < 32);
 
-	uint32_t mask = UINT32_C(1) << nr;
+	uint32_t mask = RTE_BIT32(nr);
 	*addr = (*addr) | mask;
 }
 
@@ -80,7 +96,7 @@  rte_bit_relaxed_clear32(unsigned int nr, volatile uint32_t *addr)
 {
 	RTE_ASSERT(nr < 32);
 
-	uint32_t mask = UINT32_C(1) << nr;
+	uint32_t mask = RTE_BIT32(nr);
 	*addr = (*addr) & (~mask);
 }
 
@@ -104,7 +120,7 @@  rte_bit_relaxed_test_and_set32(unsigned int nr, volatile uint32_t *addr)
 {
 	RTE_ASSERT(nr < 32);
 
-	uint32_t mask = UINT32_C(1) << nr;
+	uint32_t mask = RTE_BIT32(nr);
 	uint32_t val = *addr;
 	*addr = val | mask;
 	return val & mask;
@@ -130,7 +146,7 @@  rte_bit_relaxed_test_and_clear32(unsigned int nr, volatile uint32_t *addr)
 {
 	RTE_ASSERT(nr < 32);
 
-	uint32_t mask = UINT32_C(1) << nr;
+	uint32_t mask = RTE_BIT32(nr);
 	uint32_t val = *addr;
 	*addr = val & (~mask);
 	return val & mask;
@@ -157,7 +173,7 @@  rte_bit_relaxed_get64(unsigned int nr, volatile uint64_t *addr)
 {
 	RTE_ASSERT(nr < 64);
 
-	uint64_t mask = UINT64_C(1) << nr;
+	uint64_t mask = RTE_BIT64(nr);
 	return (*addr) & mask;
 }
 
@@ -178,7 +194,7 @@  rte_bit_relaxed_set64(unsigned int nr, volatile uint64_t *addr)
 {
 	RTE_ASSERT(nr < 64);
 
-	uint64_t mask = UINT64_C(1) << nr;
+	uint64_t mask = RTE_BIT64(nr);
 	(*addr) = (*addr) | mask;
 }
 
@@ -199,7 +215,7 @@  rte_bit_relaxed_clear64(unsigned int nr, volatile uint64_t *addr)
 {
 	RTE_ASSERT(nr < 64);
 
-	uint64_t mask = UINT64_C(1) << nr;
+	uint64_t mask = RTE_BIT64(nr);
 	*addr = (*addr) & (~mask);
 }
 
@@ -223,7 +239,7 @@  rte_bit_relaxed_test_and_set64(unsigned int nr, volatile uint64_t *addr)
 {
 	RTE_ASSERT(nr < 64);
 
-	uint64_t mask = UINT64_C(1) << nr;
+	uint64_t mask = RTE_BIT64(nr);
 	uint64_t val = *addr;
 	*addr = val | mask;
 	return val;
@@ -249,7 +265,7 @@  rte_bit_relaxed_test_and_clear64(unsigned int nr, volatile uint64_t *addr)
 {
 	RTE_ASSERT(nr < 64);
 
-	uint64_t mask = UINT64_C(1) << nr;
+	uint64_t mask = RTE_BIT64(nr);
 	uint64_t val = *addr;
 	*addr = val & (~mask);
 	return val & mask;