diff mbox series

[v2,14/17] distributor: add checks for max SIMD bitwidth

Message ID	20200827161304.32300-15-ciara.power@intel.com (mailing list archive)
State	Superseded, archived
Delegated to:	David Marchand
Headers	IronPort-SDR: o6f9i/8hhkMvFX9ft/jlNmdWCVHtuCwxGfznR4FtUFMbFCBTGPsG0lV9rTsdY4uFBFQYieqIBL IhyWu5gaN60w== IronPort-SDR: jSO74S3m6cdMAWdAIwX1ywVQ5GQAp90CGcx8qvOJmK+UJGvtgC8JmlEEZ3UIUpUzSYwCS0D0qZ k4ZMWFyHC+8Q== From: Ciara Power <ciara.power@intel.com> To: dev@dpdk.org Cc: Ciara Power <ciara.power@intel.com>, David Hunt <david.hunt@intel.com> Date: Thu, 27 Aug 2020 17:13:01 +0100 Message-Id: <20200827161304.32300-15-ciara.power@intel.com> In-Reply-To: <20200827161304.32300-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200827161304.32300-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v2 14/17] distributor: add checks for max SIMD bitwidth Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	add max SIMD bitwidth to EAL \| [v2,00/17] add max SIMD bitwidth to EAL [v2,01/17] eal: add max SIMD bitwidth [v2,02/17] eal: add default SIMD bitwidth values [v2,03/17] doc: add detail on using max SIMD bitwidth [v2,04/17] net/i40e: add checks for max SIMD bitwidth [v2,05/17] net/axgbe: add checks for max SIMD bitwidth [v2,06/17] net/bnxt: add checks for max SIMD bitwidth [v2,07/17] net/enic: add checks for max SIMD bitwidth [v2,08/17] net/fm10k: add checks for max SIMD bitwidth [v2,09/17] net/iavf: add checks for max SIMD bitwidth [v2,10/17] net/ice: add checks for max SIMD bitwidth [v2,11/17] net/ixgbe: add checks for max SIMD bitwidth [v2,12/17] net/mlx5: add checks for max SIMD bitwidth [v2,13/17] net/virtio: add checks for max SIMD bitwidth [v2,14/17] distributor: add checks for max SIMD bitwidth [v2,15/17] member: add checks for max SIMD bitwidth [v2,16/17] efd: add checks for max SIMD bitwidth [v2,17/17] net: add checks for max SIMD bitwidth

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Power, Ciara Aug. 27, 2020, 4:13 p.m. UTC

  When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path.

Cc: David Hunt <david.hunt@intel.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>
---
 lib/librte_distributor/rte_distributor.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/lib/librte_distributor/rte_distributor.c b/lib/librte_distributor/rte_distributor.c
index 1c047f065a..9f0a9b1d48 100644
--- a/lib/librte_distributor/rte_distributor.c
+++ b/lib/librte_distributor/rte_distributor.c
@@ -636,7 +636,8 @@  rte_distributor_create(const char *name,
 
 	d->dist_match_fn = RTE_DIST_MATCH_SCALAR;
 #if defined(RTE_ARCH_X86)
-	d->dist_match_fn = RTE_DIST_MATCH_VECTOR;
+	if (rte_get_max_simd_bitwidth() >= RTE_MAX_128_SIMD)
+		d->dist_match_fn = RTE_DIST_MATCH_VECTOR;
 #endif
 
 	/*