diff mbox series

[v2] eal: add new prefetch write variants

Message ID 20200914151021.23806-1-harry.van.haaren@intel.com (mailing list archive)
State Superseded, archived
Delegated to: David Marchand
Headers
Series [v2] eal: add new prefetch write variants |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-testing success Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/travis-robot success Travis build: passed
ci/iol-mellanox-Performance success Performance Testing PASS
ci/Intel-compilation success Compilation OK

Commit Message

Van Haaren, Harry Sept. 14, 2020, 3:10 p.m. UTC 
  This commit adds a new rte_prefetch0_write() variants, suggesting to the
compiler to use a prefetch instruction with intention to write. As a
compiler builtin, the compiler can choose based on compilation target
what the best implementation for this instruction is.

Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>

---

v2:
- Add L1, L2, and L3 variants as ARM64 uarch supports them (Pavan)

The integer constants passed to the builtin are not available as
a #define value, and doing #defines just for this write variant
does not seems a nice solution to me... particularly for those using
IDEs where any #define value is auto-hinted for code-completion.
---
 lib/librte_eal/include/generic/rte_prefetch.h | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)

Comments

David Marchand Oct. 8, 2020, 7:42 a.m. UTC | #1 
On Mon, Sep 14, 2020 at 5:09 PM Harry van Haaren
<harry.van.haaren@intel.com> wrote:
>
> This commit adds a new rte_prefetch0_write() variants, suggesting to the
> compiler to use a prefetch instruction with intention to write. As a
> compiler builtin, the compiler can choose based on compilation target
> what the best implementation for this instruction is.
>
> Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>

No review, copying arch maintainers.
Van Haaren, Harry Oct. 8, 2020, 8:34 a.m. UTC | #2 
> -----Original Message-----
> From: David Marchand <david.marchand@redhat.com>
> Sent: Thursday, October 8, 2020 8:43 AM
> To: Van Haaren, Harry <harry.van.haaren@intel.com>; Richardson, Bruce
> <bruce.richardson@intel.com>; Ananyev, Konstantin
> <konstantin.ananyev@intel.com>; Jerin Jacob Kollanukkaran <jerinj@marvell.com>;
> Ruifeng Wang (Arm Technology China) <ruifeng.wang@arm.com>; Jan Viktorin
> <viktorin@rehivetech.com>; David Christensen <drc@linux.vnet.ibm.com>;
> Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Cc: dev <dev@dpdk.org>; Pavan Nikhilesh <pbhagavatula@marvell.com>
> Subject: Re: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants
> 
> On Mon, Sep 14, 2020 at 5:09 PM Harry van Haaren
> <harry.van.haaren@intel.com> wrote:
> >
> > This commit adds a new rte_prefetch0_write() variants, suggesting to the
> > compiler to use a prefetch instruction with intention to write. As a
> > compiler builtin, the compiler can choose based on compilation target
> > what the best implementation for this instruction is.
> >
> > Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
> 
> No review, copying arch maintainers.
> 
> --
> David Marchand

Hey All,

Actually Pavan provided some feedback to add prefetch1 and prefetch2 variants:
https://mails.dpdk.org/archives/dev/2020-September/thread.html#180501

I can push a v3 with those changes later today, will CC folks here.

Thanks, -Harry
Van Haaren, Harry Oct. 8, 2020, 8:39 a.m. UTC | #3 
> -----Original Message-----
> From: Van Haaren, Harry
> Sent: Thursday, October 8, 2020 9:34 AM
> To: David Marchand <david.marchand@redhat.com>; Richardson, Bruce
> <bruce.richardson@intel.com>; Ananyev, Konstantin
> <konstantin.ananyev@intel.com>; Jerin Jacob Kollanukkaran <jerinj@marvell.com>;
> Ruifeng Wang (Arm Technology China) <ruifeng.wang@arm.com>; Jan Viktorin
> <viktorin@rehivetech.com>; David Christensen <drc@linux.vnet.ibm.com>;
> Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Cc: dev <dev@dpdk.org>; Pavan Nikhilesh <pbhagavatula@marvell.com>
> Subject: RE: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants
> 
> > -----Original Message-----
> > From: David Marchand <david.marchand@redhat.com>
> > Sent: Thursday, October 8, 2020 8:43 AM
> > To: Van Haaren, Harry <harry.van.haaren@intel.com>; Richardson, Bruce
> > <bruce.richardson@intel.com>; Ananyev, Konstantin
> > <konstantin.ananyev@intel.com>; Jerin Jacob Kollanukkaran
> <jerinj@marvell.com>;
> > Ruifeng Wang (Arm Technology China) <ruifeng.wang@arm.com>; Jan Viktorin
> > <viktorin@rehivetech.com>; David Christensen <drc@linux.vnet.ibm.com>;
> > Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> > Cc: dev <dev@dpdk.org>; Pavan Nikhilesh <pbhagavatula@marvell.com>
> > Subject: Re: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants
> >
> > On Mon, Sep 14, 2020 at 5:09 PM Harry van Haaren
> > <harry.van.haaren@intel.com> wrote:
> > >
> > > This commit adds a new rte_prefetch0_write() variants, suggesting to the
> > > compiler to use a prefetch instruction with intention to write. As a
> > > compiler builtin, the compiler can choose based on compilation target
> > > what the best implementation for this instruction is.
> > >
> > > Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
> >
> > No review, copying arch maintainers.
> >
> > --
> > David Marchand
> 
> Hey All,
> 
> Actually Pavan provided some feedback to add prefetch1 and prefetch2 variants:
> https://mails.dpdk.org/archives/dev/2020-September/thread.html#180501
> 
> I can push a v3 with those changes later today, will CC folks here.
> 
> Thanks, -Harry

... apologies - David you're right - the v2 on list already has those changes: http://patches.dpdk.org/patch/77632/ reviews welcome!
Jerin Jacob Oct. 8, 2020, 8:54 a.m. UTC | #4 
On Mon, Sep 14, 2020 at 8:39 PM Harry van Haaren
<harry.van.haaren@intel.com> wrote:
>
> This commit adds a new rte_prefetch0_write() variants, suggesting to the
> compiler to use a prefetch instruction with intention to write. As a
> compiler builtin, the compiler can choose based on compilation target
> what the best implementation for this instruction is.
>
> Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
>
> ---
>
> v2:
> - Add L1, L2, and L3 variants as ARM64 uarch supports them (Pavan)
>
> The integer constants passed to the builtin are not available as
> a #define value, and doing #defines just for this write variant
> does not seems a nice solution to me... particularly for those using
> IDEs where any #define value is auto-hinted for code-completion.
> ---
>  lib/librte_eal/include/generic/rte_prefetch.h | 49 +++++++++++++++++++
>  1 file changed, 49 insertions(+)
>
> diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h
> index 6e47bdfbad..3dfca77a74 100644
> --- a/lib/librte_eal/include/generic/rte_prefetch.h
> +++ b/lib/librte_eal/include/generic/rte_prefetch.h
> @@ -51,4 +51,53 @@ static inline void rte_prefetch2(const volatile void *p);
>   */
>  static inline void rte_prefetch_non_temporal(const volatile void *p);
>
> +/**
> + * Prefetch a cache line into all cache levels, with intention to write. This
> + * prefetch variant hints to the CPU that the program is expecting to write to
> + * the cache line being prefetched.
> + *
> + * @param p Address to prefetch
> + */
> +static inline void rte_prefetch0_write(const void *p)

Typically DPDK coding standards is to have

static inline void
rte_prefetch0_write(const void *p)

vs
static inline void rte_prefetch0_write(const void *p)

Either way:

Reviewed-by: Jerin Jacob <jerinj@marvell.com>


> +{
> +       /* 1 indicates intention to write, 3 sets target cache level to L1. See
> +        * GCC docs where these integer constants are described in more detail:
> +        *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
> +        */
> +       __builtin_prefetch(p, 1, 3);
> +}
> +
> +/**
> + * Prefetch a cache line into all cache levels, except the 0th, with intention
> + * to write. This prefetch variant hints to the CPU that the program is
> + * expecting to write to the cache line being prefetched.
> + *
> + * @param p Address to prefetch
> + */
> +static inline void rte_prefetch1_write(const void *p)
> +{
> +       /* 1 indicates intention to write, 2 sets target cache level to L2. See
> +        * GCC docs where these integer constants are described in more detail:
> +        *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
> +        */
> +       __builtin_prefetch(p, 1, 2);
> +}
> +
> +/**
> + * Prefetch a cache line into all cache levels, except the 0th and 1st, with
> + * intention to write. This prefetch variant hints to the CPU that the program
> + * is expecting to write to the cache line being prefetched.
> + *
> + * @param p Address to prefetch
> + */
> +static inline void rte_prefetch2_write(const void *p)
> +{
> +       /* 1 indicates intention to write, 1 sets target cache level to L3. See
> +        * GCC docs where these integer constants are described in more detail:
> +        *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
> +        */
> +       __builtin_prefetch(p, 1, 1);
> +}
> +
> +
>  #endif /* _RTE_PREFETCH_H_ */
> --
> 2.17.1
>
Ruifeng Wang Oct. 10, 2020, 10:21 a.m. UTC | #5 
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Harry van Haaren
> Sent: Monday, September 14, 2020 11:10 PM
> To: dev@dpdk.org
> Cc: pbhagavatula@marvell.com; Harry van Haaren
> <harry.van.haaren@intel.com>
> Subject: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants
> 
> This commit adds a new rte_prefetch0_write() variants, suggesting to the
> compiler to use a prefetch instruction with intention to write. As a compiler
> builtin, the compiler can choose based on compilation target what the best
> implementation for this instruction is.
> 
> Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
> 
> ---
> 
> v2:
> - Add L1, L2, and L3 variants as ARM64 uarch supports them (Pavan)
> 
> The integer constants passed to the builtin are not available as a #define
> value, and doing #defines just for this write variant does not seems a nice
> solution to me... particularly for those using IDEs where any #define value is
> auto-hinted for code-completion.
> ---
>  lib/librte_eal/include/generic/rte_prefetch.h | 49 +++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/lib/librte_eal/include/generic/rte_prefetch.h
> b/lib/librte_eal/include/generic/rte_prefetch.h
> index 6e47bdfbad..3dfca77a74 100644
> --- a/lib/librte_eal/include/generic/rte_prefetch.h
> +++ b/lib/librte_eal/include/generic/rte_prefetch.h
> @@ -51,4 +51,53 @@ static inline void rte_prefetch2(const volatile void *p);
>   */
>  static inline void rte_prefetch_non_temporal(const volatile void *p);
> 
> +/**
> + * Prefetch a cache line into all cache levels, with intention to
> +write. This
> + * prefetch variant hints to the CPU that the program is expecting to
> +write to
> + * the cache line being prefetched.
> + *
> + * @param p Address to prefetch
> + */
> +static inline void rte_prefetch0_write(const void *p) {
> +	/* 1 indicates intention to write, 3 sets target cache level to L1. See
> +	 * GCC docs where these integer constants are described in more
> detail:
> +	 *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
> +	 */
> +	__builtin_prefetch(p, 1, 3);
> +}
> +
> +/**
> + * Prefetch a cache line into all cache levels, except the 0th, with
> +intention
> + * to write. This prefetch variant hints to the CPU that the program is
> + * expecting to write to the cache line being prefetched.
> + *
> + * @param p Address to prefetch
> + */
> +static inline void rte_prefetch1_write(const void *p) {
> +	/* 1 indicates intention to write, 2 sets target cache level to L2. See
> +	 * GCC docs where these integer constants are described in more
> detail:
> +	 *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
> +	 */
> +	__builtin_prefetch(p, 1, 2);
> +}
> +
> +/**
> + * Prefetch a cache line into all cache levels, except the 0th and 1st,
> +with
> + * intention to write. This prefetch variant hints to the CPU that the
> +program
> + * is expecting to write to the cache line being prefetched.
> + *
> + * @param p Address to prefetch
> + */
> +static inline void rte_prefetch2_write(const void *p) {
> +	/* 1 indicates intention to write, 1 sets target cache level to L3. See
> +	 * GCC docs where these integer constants are described in more
> detail:
> +	 *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
> +	 */
> +	__builtin_prefetch(p, 1, 1);
> +}
> +
> +
>  #endif /* _RTE_PREFETCH_H_ */
> --
> 2.17.1

Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
David Marchand Oct. 15, 2020, 8:18 a.m. UTC | #6 
Hello Harry,

On Mon, Sep 14, 2020 at 5:09 PM Harry van Haaren
<harry.van.haaren@intel.com> wrote:
>
> This commit adds a new rte_prefetch0_write() variants, suggesting to the
> compiler to use a prefetch instruction with intention to write. As a
> compiler builtin, the compiler can choose based on compilation target
> what the best implementation for this instruction is.
>
> Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>

There was a small comment from Jerin.

Those are new functions and should be marked as experimental.
Please add a call to those in test_prefetch.c.
Please update the release notes.

Thanks.
Van Haaren, Harry Oct. 15, 2020, 8:44 a.m. UTC | #7 
> -----Original Message-----
> From: David Marchand <david.marchand@redhat.com>
> Sent: Thursday, October 15, 2020 9:18 AM
> To: Van Haaren, Harry <harry.van.haaren@intel.com>
> Cc: dev <dev@dpdk.org>; Pavan Nikhilesh <pbhagavatula@marvell.com>; Jerin
> Jacob Kollanukkaran <jerinj@marvell.com>; Ruifeng Wang (Arm Technology
> China) <ruifeng.wang@arm.com>
> Subject: Re: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants
> 
> Hello Harry,
> 
> On Mon, Sep 14, 2020 at 5:09 PM Harry van Haaren
> <harry.van.haaren@intel.com> wrote:
> >
> > This commit adds a new rte_prefetch0_write() variants, suggesting to the
> > compiler to use a prefetch instruction with intention to write. As a
> > compiler builtin, the compiler can choose based on compilation target
> > what the best implementation for this instruction is.
> >
> > Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
> 
> There was a small comment from Jerin.
> 
> Those are new functions and should be marked as experimental.
> Please add a call to those in test_prefetch.c.
> Please update the release notes.

Will do - thanks!
diff mbox series

Patch

diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h
index 6e47bdfbad..3dfca77a74 100644
--- a/lib/librte_eal/include/generic/rte_prefetch.h
+++ b/lib/librte_eal/include/generic/rte_prefetch.h
@@ -51,4 +51,53 @@  static inline void rte_prefetch2(const volatile void *p);
  */
 static inline void rte_prefetch_non_temporal(const volatile void *p);
 
+/**
+ * Prefetch a cache line into all cache levels, with intention to write. This
+ * prefetch variant hints to the CPU that the program is expecting to write to
+ * the cache line being prefetched.
+ *
+ * @param p Address to prefetch
+ */
+static inline void rte_prefetch0_write(const void *p)
+{
+	/* 1 indicates intention to write, 3 sets target cache level to L1. See
+	 * GCC docs where these integer constants are described in more detail:
+	 *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
+	 */
+	__builtin_prefetch(p, 1, 3);
+}
+
+/**
+ * Prefetch a cache line into all cache levels, except the 0th, with intention
+ * to write. This prefetch variant hints to the CPU that the program is
+ * expecting to write to the cache line being prefetched.
+ *
+ * @param p Address to prefetch
+ */
+static inline void rte_prefetch1_write(const void *p)
+{
+	/* 1 indicates intention to write, 2 sets target cache level to L2. See
+	 * GCC docs where these integer constants are described in more detail:
+	 *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
+	 */
+	__builtin_prefetch(p, 1, 2);
+}
+
+/**
+ * Prefetch a cache line into all cache levels, except the 0th and 1st, with
+ * intention to write. This prefetch variant hints to the CPU that the program
+ * is expecting to write to the cache line being prefetched.
+ *
+ * @param p Address to prefetch
+ */
+static inline void rte_prefetch2_write(const void *p)
+{
+	/* 1 indicates intention to write, 1 sets target cache level to L3. See
+	 * GCC docs where these integer constants are described in more detail:
+	 *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
+	 */
+	__builtin_prefetch(p, 1, 1);
+}
+
+
 #endif /* _RTE_PREFETCH_H_ */