diff mbox series

[v9,17/18] node: choose vector path at runtime

Message ID	20201016142742.87297-18-ciara.power@intel.com (mailing list archive)
State	Superseded, archived
Delegated to:	David Marchand
Headers	IronPort-SDR: DsbYtCna5ABvnTpiGnTcAB1XJvSecfF28j9zBjBmumnJLXb1Ld0jVivqLbD8VqNrIzuXww5XYS pix9SBgbcrJw== IronPort-SDR: HgY/M4P/vZiH1mGcjRR6EFN/QbfTXCQtYru0G3BEtNfQYzzVlNwpNXpXEn2E2S9dIaGiUqSDrn SdSDwENPibtg== From: Ciara Power <ciara.power@intel.com> To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, david.marchand@redhat.com, Ciara Power <ciara.power@intel.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, Kiran Kumar K <kirankumark@marvell.com> Date: Fri, 16 Oct 2020 15:27:41 +0100 Message-Id: <20201016142742.87297-18-ciara.power@intel.com> In-Reply-To: <20201016142742.87297-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201016142742.87297-1-ciara.power@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v9 17/18] node: choose vector path at runtime Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	add max SIMD bitwidth to EAL \| [v9,00/18] add max SIMD bitwidth to EAL [v9,01/18] eal: add max SIMD bitwidth [v9,02/18] doc: add detail on using max SIMD bitwidth [v9,03/18] net/i40e: add checks for max SIMD bitwidth [v9,04/18] net/axgbe: add checks for max SIMD bitwidth [v9,05/18] net/bnxt: add checks for max SIMD bitwidth [v9,06/18] net/enic: add checks for max SIMD bitwidth [v9,07/18] net/fm10k: add checks for max SIMD bitwidth [v9,08/18] net/iavf: add checks for max SIMD bitwidth [v9,09/18] net/ice: add checks for max SIMD bitwidth [v9,10/18] net/ixgbe: add checks for max SIMD bitwidth [v9,11/18] net/mlx5: add checks for max SIMD bitwidth [v9,12/18] net/virtio: add checks for max SIMD bitwidth [v9,13/18] distributor: add checks for max SIMD bitwidth [v9,14/18] member: add checks for max SIMD bitwidth [v9,15/18] efd: add checks for max SIMD bitwidth [v9,16/18] net: add checks for max SIMD bitwidth [v9,17/18] node: choose vector path at runtime [v9,18/18] acl: add checks for max SIMD bitwidth

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Power, Ciara Oct. 16, 2020, 2:27 p.m. UTC

  When choosing the vector path, max SIMD bitwidth is now checked to
ensure the vector path is suitable. To do this, the scalar function is
chosen by default in the struct, but at node initialisation time, this
function pointer is updated to the vector version if supported, and
if it is within the max SIMD bitwidth limit.

Cc: Nithin Dabilpuram <ndabilpuram@marvell.com>
Cc: Pavan Nikhilesh <pbhagavatula@marvell.com>
Cc: Jerin Jacob <jerinj@marvell.com>
Cc: Kiran Kumar K <kirankumark@marvell.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

---
v6:
  - Removed generic process function.
  - Change the process function pointer at node init time to vector
    function if suitable.
---
 lib/librte_node/ip4_lookup.c      | 14 +++++++++-----
 lib/librte_node/ip4_lookup_neon.h |  2 +-
 lib/librte_node/ip4_lookup_sse.h  |  2 +-
 3 files changed, 11 insertions(+), 7 deletions(-)

diff mbox series

Patch

diff --git a/lib/librte_node/ip4_lookup.c b/lib/librte_node/ip4_lookup.c
index 293c77f39e..934a6d7eab 100644
--- a/lib/librte_node/ip4_lookup.c
+++ b/lib/librte_node/ip4_lookup.c
@@ -34,10 +34,10 @@  static struct ip4_lookup_node_main ip4_lookup_nm;
 #include "ip4_lookup_neon.h"
 #elif defined(RTE_ARCH_X86)
 #include "ip4_lookup_sse.h"
-#else
+#endif
 
 static uint16_t
-ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node,
+ip4_lookup_node_process_scalar(struct rte_graph *graph, struct rte_node *node,
 			void **objs, uint16_t nb_objs)
 {
 	struct rte_ipv4_hdr *ipv4_hdr;
@@ -109,8 +109,6 @@  ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node,
 	return nb_objs;
 }
 
-#endif
-
 int
 rte_node_ip4_route_add(uint32_t ip, uint8_t depth, uint16_t next_hop,
 		       enum rte_node_ip4_lookup_next next_node)
@@ -194,13 +192,19 @@  ip4_lookup_node_init(const struct rte_graph *graph, struct rte_node *node)
 		init_once = 1;
 	}
 	*lpm_p = ip4_lookup_nm.lpm_tbl[graph->socket];
+
+#if defined(__ARM_NEON) || defined(RTE_ARCH_X86)
+	if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128)
+		node->process = ip4_lookup_node_process_vec;
+#endif
+
 	node_dbg("ip4_lookup", "Initialized ip4_lookup node");
 
 	return 0;
 }
 
 static struct rte_node_register ip4_lookup_node = {
-	.process = ip4_lookup_node_process,
+	.process = ip4_lookup_node_process_scalar,
 	.name = "ip4_lookup",
 
 	.init = ip4_lookup_node_init,
diff --git a/lib/librte_node/ip4_lookup_neon.h b/lib/librte_node/ip4_lookup_neon.h
index 5e5a7d87be..0ad2763b82 100644
--- a/lib/librte_node/ip4_lookup_neon.h
+++ b/lib/librte_node/ip4_lookup_neon.h
@@ -7,7 +7,7 @@ 
 
 /* ARM64 NEON */
 static uint16_t
-ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node,
+ip4_lookup_node_process_vec(struct rte_graph *graph, struct rte_node *node,
 			void **objs, uint16_t nb_objs)
 {
 	struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3, **pkts;
diff --git a/lib/librte_node/ip4_lookup_sse.h b/lib/librte_node/ip4_lookup_sse.h
index a071cc5919..264c986071 100644
--- a/lib/librte_node/ip4_lookup_sse.h
+++ b/lib/librte_node/ip4_lookup_sse.h
@@ -7,7 +7,7 @@ 
 
 /* X86 SSE */
 static uint16_t
-ip4_lookup_node_process(struct rte_graph *graph, struct rte_node *node,
+ip4_lookup_node_process_vec(struct rte_graph *graph, struct rte_node *node,
 			void **objs, uint16_t nb_objs)
 {
 	struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3, **pkts;