From patchwork Fri Oct 23 18:30:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timothy McDaniel X-Patchwork-Id: 81967 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 23EF8A04DD; Fri, 23 Oct 2020 20:30:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AE18C677C; Fri, 23 Oct 2020 20:28:51 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id D4C275AA1 for ; Fri, 23 Oct 2020 20:28:40 +0200 (CEST) IronPort-SDR: o2ZaJ+tcLlzgdrSHsepevrFSexNjAinSbfcon3Ou+ACMqF/naNu76za5GKrTjhwMWJ/0n9AYdH ubjScGco8PiQ== X-IronPort-AV: E=McAfee;i="6000,8403,9783"; a="229351135" X-IronPort-AV: E=Sophos;i="5.77,409,1596524400"; d="scan'208";a="229351135" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2020 11:28:38 -0700 IronPort-SDR: F67m8d53yduyhPW9Tl4Sd3CxdkIui74HwD6V12LYAPsRCaERTfgh4IoZotOMi4vk01p1opEQdP zUacSnJZkZOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,409,1596524400"; d="scan'208";a="524763999" Received: from txasoft-yocto.an.intel.com ([10.123.72.192]) by fmsmga005.fm.intel.com with ESMTP; 23 Oct 2020 11:28:37 -0700 From: Timothy McDaniel To: Cc: dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com, harry.van.haaren@intel.com, jerinj@marvell.com Date: Fri, 23 Oct 2020 13:30:08 -0500 Message-Id: <1603477826-31374-6-git-send-email-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1603477826-31374-1-git-send-email-timothy.mcdaniel@intel.com> References: <1599855987-25976-2-git-send-email-timothy.mcdaniel@intel.com> <1603477826-31374-1-git-send-email-timothy.mcdaniel@intel.com> Subject: [dpdk-dev] [PATCH v3 05/23] event/dlb2: add inline functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add miscellaneous inline functions that may be called from multiple files. These functions include inline assembly of new x86 instructions, such as movdir64b, since they are not available as builtin functions in the minimum supported GCC version. Signed-off-by: Timothy McDaniel Reviewed-by: Gage Eads --- drivers/event/dlb2/dlb2_inline_fns.h | 61 ++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 drivers/event/dlb2/dlb2_inline_fns.h diff --git a/drivers/event/dlb2/dlb2_inline_fns.h b/drivers/event/dlb2/dlb2_inline_fns.h new file mode 100644 index 0000000..ccbc4f4 --- /dev/null +++ b/drivers/event/dlb2/dlb2_inline_fns.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2016-2020 Intel Corporation + */ + +#ifndef _DLB2_INLINE_FNS_H_ +#define _DLB2_INLINE_FNS_H_ + +/* Inline functions required in more than one source file. */ + +static inline struct dlb2_eventdev * +dlb2_pmd_priv(const struct rte_eventdev *eventdev) +{ + return eventdev->data->dev_private; +} + +static inline void +dlb2_umonitor(volatile void *addr) +{ + asm volatile(".byte 0xf3, 0x0f, 0xae, 0xf7\t\n" + : + : "D" (addr)); +} + +static inline void +dlb2_umwait(int state, uint64_t timeout) +{ + uint32_t eax = timeout & UINT32_MAX; + uint32_t edx = timeout >> 32; + + asm volatile(".byte 0xf2, 0x0f, 0xae, 0xf7\t\n" + : + : "D" (state), "a" (eax), "d" (edx)); +} + +static inline void +dlb2_movntdq_single(void *pp_addr, void *qe4) +{ + long long *_qe = (long long *)qe4; + __v2di src_data0 = (__v2di){_qe[0], _qe[1]}; + + __builtin_ia32_movntdq((__v2di *)pp_addr, (__v2di)src_data0); +} + +static inline void +dlb2_cldemote(void *addr) +{ + /* Load addr into RSI, then demote the cache line of the address + * contained in that register. + */ + asm volatile(".byte 0x0f, 0x1c, 0x06" :: "S" (addr)); +} + +static inline void +dlb2_movdir64b(void *pp_addr, void *qe4) +{ + asm volatile(".byte 0x66, 0x0f, 0x38, 0xf8, 0x02" + : + : "a" (pp_addr), "d" (qe4)); +} + +#endif /* _DLB2_INLINE_FNS_H_ */