[v13,12/12] config: fix Arm implementer and its SoCs
diff mbox series

Message ID 1605874101-30893-13-git-send-email-juraj.linkes@pantheon.tech
State New
Delegated to: Thomas Monjalon
Headers show
Series
  • Arm build options rework
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ci/Intel-compilation success Compilation OK
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-testing warning Testing issues
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/checkpatch success coding style OK

Commit Message

Juraj Linkeš Nov. 20, 2020, 12:08 p.m. UTC
Fix the implementer and part number of DPAA and ARMADA SoCs.
The current values of 16 cores and 1 NUMA node don't cover all SoCs from
the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.
Increase these to 64 and 4 to widen the coverage.
Add configuration to SoC options where smaller values are needed.

Fixes: 6ec78c2463ac ("build: add meson support for dpaaX platforms")
Cc: hemant.agrawal@nxp.com
Fixes: dd1cd845c102 ("config: add Marvell ARMADA based on armv8-a")
Cc: lironh@marvell.com
Fixes: d97108a33231 ("config: change defaults of armv8")
Cc: yskoh@mellanox.com

Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
---
 config/arm/meson.build | 54 ++++++++++++++++++------------------------
 1 file changed, 23 insertions(+), 31 deletions(-)

Patch
diff mbox series

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 94a7dd295..3f15000ff 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -74,8 +74,8 @@  implementer_arm = {
 		['RTE_MACHINE', '"armv8a"'],
 		['RTE_USE_C11_MEM_MODEL', true],
 		['RTE_CACHE_LINE_SIZE', 64],
-		['RTE_MAX_LCORE', 16],
-		['RTE_MAX_NUMA_NODES', 1]
+		['RTE_MAX_LCORE', 64],
+		['RTE_MAX_NUMA_NODES', 4]
 	],
 	'part_number_config': part_number_config_arm
 }
@@ -145,38 +145,12 @@  implementer_ampere = {
 	}
 }
 
-implementer_marvell = {
-	'description': 'Marvell ARMADA',
-	'flags': [
-		['RTE_MACHINE', '"armv8a"'],
-		['RTE_CACHE_LINE_SIZE', 64],
-		['RTE_MAX_LCORE', 16],
-		['RTE_MAX_NUMA_NODES', 1]
-	],
-	'part_number_config': part_number_config_arm
-}
-
-implementer_dpaa = {
-	'description': 'NXP DPAA',
-	'flags': [
-		['RTE_MACHINE', '"dpaa"'],
-		['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
-		['RTE_USE_C11_MEM_MODEL', true],
-		['RTE_CACHE_LINE_SIZE', 64],
-		['RTE_MAX_LCORE', 16],
-		['RTE_MAX_NUMA_NODES', 1]
-	],
-	'part_number_config': part_number_config_arm
-}
-
 ## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
 implementers = {
 	'generic': implementer_generic,
 	'0x41': implementer_arm,
 	'0x43': implementer_cavium,
-	'0x50': implementer_ampere,
-	'0x56': implementer_marvell,
-	'dpaa': implementer_dpaa
+	'0x50': implementer_ampere
 }
 
 # soc specific aarch64 flags have the highest priority
@@ -189,8 +163,12 @@  soc_generic = {
 
 soc_armada = {
 	'description': 'Marvell ARMADA',
-	'implementer': '0x56',
+	'implementer': '0x41',
 	'part_number': '0xd08',
+	'flags': [
+		['RTE_MAX_LCORE', 16],
+		['RTE_MAX_NUMA_NODES', 1]
+	],
 	'numa': false,
 	'disabled_drivers': ['bus/dpaa', 'bus/fslmc', 'common/dpaax']
 }
@@ -199,13 +177,23 @@  soc_bluefield = {
 	'description': 'NVIDIA BlueField',
 	'implementer': '0x41',
 	'part_number': '0xd08',
+	'flags': [
+		['RTE_MAX_LCORE', 16],
+		['RTE_MAX_NUMA_NODES', 1]
+	],
 	'numa': false
 }
 
 soc_dpaa = {
 	'description': 'NXP DPAA',
-	'implementer': 'dpaa',
+	'implementer': '0x41',
 	'part_number': '0xd08',
+	'flags': [
+		['RTE_MACHINE', '"dpaa"'],
+		['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
+		['RTE_MAX_LCORE', 16],
+		['RTE_MAX_NUMA_NODES', 1]
+	],
 	'numa': false
 }
 
@@ -242,6 +230,10 @@  soc_octeontx2 = {
 soc_stingray = {
 	'description': 'Broadcom Stingray',
 	'implementer': '0x41',
+	'flags': [
+		['RTE_MAX_LCORE', 16],
+		['RTE_MAX_NUMA_NODES', 1]
+	],
 	'part_number': '0xd08',
 	'numa': false
 }